參數(shù)資料
型號(hào): TMXF84622
英文描述: TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper
中文描述: TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper
文件頁數(shù): 7/62頁
文件大?。?/td> 902K
代理商: TMXF84622
Agere Systems Inc.
7
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
Features
(continued)
I
DataLink (DS1-ESF DL) and SSM (E1 multiframe
Sa) fields read/writable.
I
Supports all Ultramapper modes of operation.
I
Complies with T1.107, T1.231, T1.403, G.703,
G.704, O.150.
CDR Features
I
Receives data at OC-12/STS-12 (622.08 Mbits/s)
data rate.
I
Single low-voltage power supply.
I
155.52 MHz or 77.76 MHz input reference clock for
on-chip PLL.
I
On-chip PLL for clock synthesis, requiring only one
external resistor, generating 16 phases, providing
resolution of ~100 ps.
I
PLL bypass mode for functional test.
I
Modular design to incorporate n = 2 to 16 channels.
I
Meets type B jitter tolerance specification of ITU-T
Recommendation G.958.
I
No output clock drift in absence of data transitions
once lock is acquired.
I
Built-in test features.
System Test and Maintenance
I
A variety of loopback modes implemented on
SONET/SDH side as well as on framer level.
I
Built-in test pattern generator and monitor config-
urable for simultaneously testing E1, DS1, DS2, E3,
DS3, and STS1 (one channel each).
Microprocessor Interface
I
21-bit address and 16-bit data interface with 16 MHz
to 66 MHz read and write access.
I
Compatible with most industry-standard processors.
Chip Testing and Maintenance
I
IEEE
* 1149.1 JTAG boundary scan.
Interface to Other Agere Devices
Seamless interface to the following Agere Systems
devices:
I
TADM042G5
I
Super Mapper
* IEEE
is a registered trademark of the Institute of Electrical and
Electronics Engineers, Inc
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