參數(shù)資料
型號(hào)： TMXF84622
英文描述： TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper
中文描述： TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper
文件頁數(shù)： 35/62頁
文件大小： 902K
代理商： TMXF84622
Agere Systems Inc.
35
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
3 Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
* O
1
indicates external pull-up recommended (unused or system required),
I/O
2
indicates external pull-down recommended (unused or system required),
I
D
; I/O
D
indicate internal pull-down,
I
U
indicates internal pull-up.
Transmit path convention is toward the high-speed fiber output. Note that CHIRX signals are labeled
“
Receive,
”
as seen from the cross con-
nect perspective.
Pin
Symbol
Type
Multifunction System Interface
(continued)
CHI Transmit PATH Direction (45 total, last 3 not indexed)
CHIRXDATA[42:1]
—
I
Configurable Inputs to the Internal Cross Connect.
Switching modes:
CHI:
Receive system data or data and signaling input at
2.048 Mbits/s
,
4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s.
I/O
*
Description
J32, J33,
H34, L30,
M29, K33,
J34, M30,
L32, K34,
L33, N29,
M32, L34,
M33, P29,
M34, P30,
N33, P32,
N34, R29,
P33, R30,
P34, R32,
T29, R33,
R34, U29,
T33, T34,
U30, U32,
U33, V33,
V32, V30,
W34, W33,
V29, Y34
Y32
Parallel system bus:
CHIRXDATA[16:1]: Receive system data bus input is assigned to
the first 16 inputs (19.44 Mbits/s). MSB
—
CHIRXDATA[16]
through LSB to CHIRXDATA[1].
CHIRXDATA[42:17]: Not used in PSB mode only.
Transport modes:
Framer
—
LIU: CHIRXDATA[30:1] Received negative-rail
DS1/E1 line data input or 8k frame sync input.
M12 or E12: not used.
VT Mapper: 8 k SYNC for DS1/E1 or 2 k sync signal for VC.
M23 or E23: Stuff request input in demand clocking mode.
CHIRXGTCLK
—
I
CHI: global transmit line clock input. Externally supplied
1.544 MHz for DS1 and 2.048 MHz low jitter clock phase-locked
to the receive CHI system clock (optional).
Parallel system bus: global transmit line clock input. Externally
supplied 1.544 MHz for DS1 and 2.048 MHz low jitter clock
phase-locked to the parallel system bus receive clock (optional).
CHI: receive global system clock input (4.096 MHz, 8.192 MHz,
or 16.384 MHz).
W29
CHIRXGCLK
—
I
Parallel system bus: Receive global clock input (19.44 MHz).
CHI: Receive system frame sync input.
Y33
CHIRXGFS
—
I
Parallel system bus: Receive system frame sync input.
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TMXF846221BL-3-DB 制造商:LSI Corporation 功能描述:Mapper DS3/E3/DS2/DS1/DS0/E1 SONET/SDH 155Mbps/622Mbps 1.5V/3.3V 700-Pin BGA Bag
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