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參數(shù)資料
| 型號： | TMXF84622 |
| 英文描述： | TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper |
| 中文描述： | TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper |
| 文件頁數(shù)： | 2/62頁 |
| 文件大?。?/td> | 902K |
| 代理商： | TMXF84622 |
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2
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
Features
(continued)
Mapping/Multiplexing Modes 84/63 (3x28/21)
I
Maps DS3 clear channel or framed signal into STS-1
or TUG-3.
I
Maps T1/E1/J1
into
VT/TU structures.
I
Maps T1
into
VT1.5/TU-11/TU-12.
I
Maps J1
into
VT1.5/TU-11/TU-12.
I
Maps E1
into
VT2/TU-12.
I
Supports asynchronous, byte-synchronous, and bit-
synchronous mapping.
I
Supports UPSR applications via the dedicated ring
interface and an external tributary selector.
I
Supports all valid T1/E1/J1 multiplexing structures
into STS-1 and STS-3/STM-1.
I
STS-3/STS-1/SPE/VTG/VTx.
I
STM-1/AU-3/TUG-2/TU-1x/VC-1x.
I
STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x.
I
Allows grooming of VTs/TUs in granularity of TUG-2s
within the STS-3/STM-1 signal.
I
Supports J2 trace identifier monitoring/insertion.
I
Configurable VT/TU slot selection for DS1, E1, J1
insertion and drop.
I
Automatic receive monitor functions include VT/TU
RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V.
I
Complies with GR-253-CORE, GR-499, ITU-T
G.707, G.704, G.783, T1.105, JT-G707, ETS 300
417-1-1.
M13 Features (3)
I
Configurable multiplexer/demultiplexer for
28 DS1 signals, 21 E1 signals, or 7 DS2 signals to/
from a DS3 signal.
I
Operates in either M23 or C-bit parity mode.
I
Provisionable time-slot selection for DS1, E1, and
DS2 insertion or drop.
I
EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit par-
ity errors, FEBE).
I
HDLC transmitter with 128-byte data buffer and
HDLC receiver with 128-byte data FIFO for the C-bit
parity path maintenance data link.
I
DS3, DS2, DS1, and E1 loopback and loopback
request generation.
I
Complies with T1.102, T1.107, T1.231, T1.403,
T1.404, GR 499, G.747, and G.775.
E13 Features (3)
I
Configurable multiplexer/demultiplexer for up to
16 E1 signals, or 4 E2 signals to/from an E3 signal.
I
Independently configurable 4 E12 multiplexer/demul-
tiplexers for up to 16 E1 signals to/from 4 E2 signals.
I
Provisionable time-slot selection for E1, E2 insertion,
or drop via the cross connect macro.
I
E12 multiplexers capable of generating alarm indica-
tion signal (AIS) and remote alarm indicator (RAI)
signals.
I
E23 multiplexer capable of generating AIS and RAI
signals.
I
Configurable HDB3 encoder/decoder for E3 output/
input.
I
E1 and E2 transmit path monitors that detect loss of
clock (LOC) and AIS.
I
E2 receive path monitor that detects LOC, AIS, and
RAI.
I
E3 receive monitor that detects loss of signal (LOS),
LOC, bipolar violation (BPV), AIS, and RAI.
I
E3 and E2 loopback modes.
I
Complies with ITU
’
s G.703, G.742, G.751, and
G.775.
DS3/DS2/DS1/E1 Cross Connect Features
I
Configurable crosspoint interconnect for up to 28 x 3
DS1 signals or 21 x 3 E1 signals to/from the framer,
30 external pins, and 28 x 3 signal channels to/from
the M13 and VT mapper. Also supports up to 7 x 3
DS2 signals to/from the external pins or M12 MUXes,
connecting to the M13 MUX M23 block.
I
Connects six clear channel DS3, E3, and STS-1 sig-
nals from the external pins to the M13, E13,
SPE_mapper, and STS1-LT.
I
Also connects three unchannelized DS3 and E3 sig-
nal to/from the external NSMI interface to the SPE,
M13, E13, framer, or TPG blocks.
I
The three NSMI
pins can also be shared for STS-1
LT
.
I
Any mix of 168 DS1, E1 signals may be intercon-
nected. Any of the available DS1/E1 signal sources
may be connected to any of 168 signal destinations
in the DS1/E1 cross connect. Multicast or broadcast
operation (one port to many) is supported for up to
168 channels. Also, any channel n at the source can
be connected to its corresponding destination chan-
nel n, where n ranges from 1 to 84 for most sources
and destinations.
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