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參數(shù)資料
| 型號： | TMXF84622 |
| 英文描述： | TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper |
| 中文描述： | TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper |
| 文件頁數(shù)： | 8/62頁 |
| 文件大?。?/td> | 902K |
| 代理商： | TMXF84622 |
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8
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
2 The SONET/SDH Ultramapper
2.1 Overview
The SONET/SDH Ultramapper device integrates the SONET/SDH line, path, and tributary termination functions
with M13/E13 multiplex functions and the primary rate framing function. It is designed to drive either an OC-12/
STM-4 or OC-3/STM-1 optical signal directly or to allow for modular growth in terminal or add/drop applications.
The Ultramapper provides a versatile interface for all STS-12/STM-4, STS-3/STM-1, and STS-1 termination appli-
cations in point-to-point scenarios and for ring applications. This chip can be used in tributary shelf applications for
up to 84 T1 or J1 or 63 E1 line cards, providing all possible mappings into SONET/SDH, because of the flexibility of
the mappings, software upgrades from M13/E13 mapped connections to VT/TU mapped connections are possible.
This device can also be used for DS3/E3/DS2 applications.
A single Ultramapper is capable of processing the aggregate bandwidth of one STS-3/STM-1 to 84/63 DS1/E1s.
Further, a single Ultramapper can process the aggregate bandwidth of two STS-3/STM-1s, terminated as an STS-
12/STM-4, to six DS3/E3s. Additionally, a single Ultramapper can function as an STS-12/STS-3/STM-4/STM-1
add-drop MUX by terminating up to three STS-1/STM-0 channels or one AU-4 channel and using the internal
pointer processors to forward any nonterminated channels. By communicating to three other mate devices via the
serial STS-3/STM-1 link interface, it is capable of terminating a full STS-12/STM-4 signal.
2351(F)
Figure 1. Functional Diagram of Ultramapper
5
S
T
S
X
C
STSPP
CDR
CDR
FRM
X84/X63
DS1/J1/E1
TPG/TPM
(X3)
X28/X21
VTMPR
(X3)
M13/E13
MUX
X6
DS3/E3
DJA
X84/X63
DS1/E1
DJA
JTAG
MPU
CDR
STS1LT
(X3)
SPEMPR
(X3)
(0
—
2)
SPEMPR
(X3)
(3
—
5)
MRXC
DS1/J1/E1
VT/TU
DS2/E2
DS3/E3
TMUX
STS12/
STM4/
STS3/
STM1
4
11
4
HIGH-SPEED IF
622 Mbits/STS12/
STM4
155 Mbits/STS-3/
STM-1
CLOCK/SYNC
MSP 1 + 1
622 Mbits/STS12/
STM4
155 Mbits/STS-3/
STM-1
4
1
JTAG IF
MPU IF
(X3)
STS3/STM1
MATE
INTERCONNECT
6
6
6
6
6
(X3)
DS3/E3 PLL IF
(OPTIONAL)
(X3)
LOPOH
(SUPPORTS UPSR)
TOAC POAC
42
RX/TX CLKS AND SYNC
8
PLL INTERFACE
SYSTEM
INTERFACES
(X6) DS3/E3
(X3) STS1
24
(X3) NSMI
(X3) STS1
204
SHARED LOW-SPEED I/O
SWITCHING MODES:
PSB (X16
—
X48/X63 DS1/J1/E1
X2016 DS0/E0
CHI (X42
—
X2016 DS0/E0
TRANSPORT MODES:
DS1/J1/E1 (X30
—
x28/x21 + PROT.
DS2/E2 (X30
—
x21/x12 + PROT.
VT/TU/(X30
—
X28/X21 + PROT.
5
X12/X4 SONET/SDH
ADM FRONT END
X8/X63 PDH
TRIBUTARY TERMINATION
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| TMXF846221BL-3-DB | 制造商:LSI Corporation 功能描述:Mapper DS3/E3/DS2/DS1/DS0/E1 SONET/SDH 155Mbps/622Mbps 1.5V/3.3V 700-Pin BGA Bag |
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