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參數(shù)資料
| 型號： | TMXF84622 |
| 英文描述： | TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper |
| 中文描述： | TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper |
| 文件頁數(shù)： | 36/62頁 |
| 文件大?。?/td> | 902K |
| 代理商： | TMXF84622 |
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36
Agere Systems Inc.
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
3 Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Pin
* O
1
indicates external pull-up recommended (unused or system required),
I/O
2
indicates external pull-down recommended (unused or system required),
I
D
; I/O
D
indicate internal pull-down, I
U
indicates internal pull-up.
Receive path convention is away from the high-speed fiber output. Note that CHITX signals are labeled Transmit, as seen from the cross con-
nect perspective.
Symbol
Type I/O
*
Description
Multifunction System Interface
(continued)
CHI Receive Path Direction (44 total, last 2 not indexed)
CHITXDATA[42:1]
—
I/O
Configurable Outputs from the Internal Cross Connect.
AA33, Y29,
AB34,
AA32,
AB33,
AA30,
AC34,
AA29,
AC33,
AD34,
AC32,
AB29,
AD33,
AE34,
AD32,
AC30,
AF34, AE33,
AC29,
AD30,
AG34,
AF33, AF32,
AH34,
AD29,
AG33,
AG32,
AE29, AJ34,
AF30, AF29,
AH33,
AK34, AJ33,
AG30,
AM34,
AJ30, AJ29,
AK29,
AP32,
AN31, AJ27
AA34
Switching modes:
CHI: Transmit system data or data and signaling output
(2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s).
Parallel system bus:
CHITXDATA[16:1]: Transmit system data bus output is restricted
to the first 16 outputs (19.44 Mbits/s). MSB
—
CHITXDATA[16] through LSB to CHITXDATA[1].
CHITXDATA[42:17]: Not used in PSB mode only.
Transport modes:
Framer
—
LIU: Transmit negative-rail DS1/E1 line data output or
8 K frame sync output.
VT mapper: 8 K sync output for DS1/E1 or 2 K sync output for VC.
M12:
CHITXDATA [7:1]: Carry DS2 data output from the M12 MUX.
CHITXDATA [14:8]: Carry DS2 clock input/output of the M12 MUX.
CHITXDATA [21:15]: Carry DS2 data input to the M12 deMUX.
CHITXDATA [28:22]: Carry DS2 clock input to the M12 deMUX.
CHITXGFS
—
I
CHI:
Transmit system frame sync input.
Parallel system bus: Transmit system frame sync input.
Switching Modes:
CHI: Transmit global system clock input
(4.096 MHz, 8.192 MHz, or 16.384 MHz).
Y30
CHITXGCLK
—
I
Parallel system bus: Transmit global clock input (19.44 MHz).
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