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參數(shù)資料
| 型號： | TMXF84622 |
| 英文描述： | TMXF84622 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper |
| 中文描述： | TMXF84622 155 Mbits/s/622 Mbits /秒接口的SONET / SDH x84/x63 Ultramapper |
| 文件頁數(shù)： | 3/62頁 |
| 文件大小： | 902K |
| 代理商： | TMXF84622 |
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Agere Systems Inc.
3
Advance Data Sheet, Rev. 2
July 2001
SONET/SDH x84/x63 Ultramapper
TMXF84622 155 Mbits/s/622 Mbits/s Interface
Features
(continued)
I
Any mix of DS2, DS3, or E3 signals may be intercon-
nected.
I
Cross connect allows 16 x 3 E1 signals to/from E13
modules to framer, M13, VT mapper, and external
pins.
I
There are 4 x 3 E2 signals to/from E13 to external
pins, TPG generator/monitor.
I
There are 3 E3 signals to/from the E13 block to
external pins, TPG generator/monitor, and SPE map-
per.
I
Jitter attenuation may also be inserted in-line on any
DS1/E1 channel. (Note that cascading of jitter atten-
uators is not allowed.)
I
Standard network loopback or straightaway facility
testing is supported for DS1/E1 and DS3/E3. Any
source or transmitter may be replaced by a test-pat-
tern generator capable of injecting idle standards-
based pseudorandom bit sequence test patterns, or
AIS (blue) alarm. Any sink or receiver may be
replaced by a test-pattern monitor, which can detect/
count bit errors in a pseudorandom test sequence, or
loss of frame or loss of synchronization.
I
One to any loopback is supported for up to
168 channels in DS1/E1 channels in blocks VT map-
per, M13, E13, and framer. One-to-one loopback is
supported in all DS1/E1 channels. One-to-one loop-
back for DS3/E3/STS-1 channels in blocks M13,
E13, and SPE mapper.
I
Loopbacks may be configured to sectionalize a cir-
cuit for identifying faults or misconfiguration during
out of service maintenance.
I
Fast alarm channels are supported for VT mapper,
E13, or M13 to framer interconnects for alarm indica-
tion signal (AIS or blue alarm), and VT mapper only
for remote alarm indicator (RAI or yellow alarm). This
feature reduces the propagation delay of the alarms
by eliminating multiple integration of alarm condi-
tions.
I
Supports framer-only, transport (framer LIU, M13,
E13, and VT mapper), and switching (CHI and PSB)
modes of operation.
I
TOAC outputs are available in DS1/E1 framed format
at any destination. Any DS1/E1 channel can be used
as TOAC inputs.
DS1/E1 Digital Jitter Attenuation Features
I
PLL-free receive operation using built-in digital jitter
attenuator (in VT/VC mode or M13 mode).
I
Configurable to meet jitter and MTIE requirements.
DS3/E3 Digital Jitter Attenuation Features
I
The PLL bandwidth, damping factor, and sampling
rates are programmable.
I
The DJA macro accepts/delivers DS3/E3 clock and
data from/to the cross connect macrocell.
T1/E1/J1 Framing Features 84/63 (3x28/21)
I
28/21 T1/E1/J1 channels.
I
Line coding: B8ZS, HDB3, ZCS, AMI, and
CMI (JJ20-11).
I
T1 framing modes: ESF, D4,
SLC
-96, T1 DM DDS,
and SF (F
t
only).
I
E1 framing: G.704 basic and CRC-4 multiframe con-
sistent with G.706.
I
J1 framing modes: JESF (Japan).
I
Supports T1 and E1 unframed and transparent trans-
mission format.
I
T1 signaling modes: transparent; register and sys-
tem access for ESF 2-state, 4-state, and 16-state;
D4 2-state, 4-state, and 16-state;
SLC
-96 2-state,
4-state, and 16-state; J-ESF handling groups mainte-
nance and signaling; VT 1.5 SPE 2-, 4-, 16-state.
I
E1 signaling modes: transparent; register and sys-
tem access for entire TS16 multiframe structure as
per ITU G.732.
I
Signaling debounce and change of state interrupt.
I
V5.2 Sa7 processing.
I
Alarm reporting and performance monitoring per
AT&T,
ANSI
, ITU-T, and ETSI standards.
I
Facility data link features:
—
HDLC or transparent access for either ESF or
DDS+ FDL frame formats.
—
Register/stack access for
SLC
-96 transmit and
receive data.
—
Extended superframe (ESF): automatic transmis-
sion of the ESF performance report messages
(PRM). Automatic transmission of the
ANSI
T1.403 ESF performance report messages.
Automatic detection and transmission of the
ANSI
T1.403 ESF FDL bit-oriented codes.
—
Register/stack access for all CEPT Sa-bits trans-
mit and receive data.
I
HDLC features:
—
HDLC or transparent mode.
—
Programmable logical channel assignment: any
time slot, any bit for ISDN D-channel, also inserts/
extracts C-channels for V5.1, V5.2 interfaces.
—
64 logical channels in both transmit and receive
direction (any framing format).
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