TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
550
Agere Systems Inc.
22 Cross Connect (XC) Block Functional Description
(continued)
22.5.1 DS1/E1 Connectivity Matrix
DS1/E1 signal connectivity matrix
Table 614
below is a subset of
Table 613, Connectivity Within the Cross Connect
Block on page 548
excluding the last row and column.
Table 614. DS1/E1 Signal Connectivity Matrix
Note:
See
Table 613, Connectivity Within the Cross Connect Block on page548
for symbol and footnote descrip-
tions.
Each box represents a set of 28 or more output bundles from the cross connect (XC) block. A bundle consists of
three standard data path signals [normally DATA, CLK, and FS or STFREQ], plus, in many cases, AUTOAIS, and,
in some cases, RAI or PTRADJ signals.
22.5.2 DS1/E1 Register Definition
For every valid output signal (bundle) from the cross connect, one input signal (bundle) to the cross connect is
steered to the destination, first via a block select (one of 8) and then via a channel select (one of 28, except exter-
nal I/O, which is one of 29). Therefore, each box in
Table 614
also represents 32 8-bit source identifiers in the reg-
ister map.
Note:
By specifying on a per-output basis, collisions are avoided and broadcast/multicast options are preserved
(that is, multiple outputs may share the same source identifier). For E1 signals, only 3 out of 4 channels are
used (channel numbers that are even multiples of four are typically disallowed).
The crosspoint
’
s connectivity is determined by a set of source identifiers (SOURCE_IDs), one for each channel
leaving the crosspoint switch. A DS1/E1 (XC1) SOURCE_ID is therefore defined as follows:
The SOURCE_BLOCK[2:0] is defined as:
The CHANNEL_ID typically ranges from 1 to 28 (29 for EXT). Values 0, 30, and 31 (and usually 29 as well) are
unused.
Destination
Source
External I/O
Framer TP_T
External
I/O
&
%
Framer
RP_R
%
T &
Framer
TP_R
%
X
Framer
RS
%
X
M13
Mapper
%
%
VT
Mapper
%
Jitter
Attenuation
%
%
TPM
T
%
2
%
X
%
T
3
T
X
T
Framer RP_T
Framer TS
M13 MUX
%
%
%
X
X
T &
X
X
X
X
X
%
X
T &
X
%
4
X
1
&
%
%
4
VT Mapper
%
%
2, 4
J
%
X
X
1
&
J
%
4, 5
T
Jitter Attenuation
J
J
X
J
X
6
T
J T
7
SELF
TPG
T
T
T
X
T
T
Bit
7
6
5
4
3
2
1
0
SOURCE_ID
SOURCE_BLOCK[2:0]
CHANNEL_ID[4:0]
Index
000
001
010
011
Block Identifier
Index
100
101
110
111
Block Identifier
VTMPR (VT Mapper)
DJA (Jitter Attenuator)
FRM RP (Framer Line Interface)
FRM TS (Framer System Interface)
TPG (Test-Pattern Generator)/Special
EXT (External I/O)
FRM TP (Superframer)
M13 (M13 MUX)