TMXF28155/51 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
372
Agere Systems Inc.
17 TMUX Functional Description
(continued)
Any change to TMUX_RLAISMON will be reported in TMUX_RLAISMOND (
Table 82, starting on page 79
) and the
interrupt can be masked using TMUX_RLAISMONM (
Table 86 on page 88
).
The TMUX monitors for a remote defect indication (RDI-L/MS-RDI) condition in the K2[2:0] bits (K2[2:0] = 110) .A
line RDI condition will be detected and TMUX_RLRDIMON (
Table 91 on page92
) will be set to 1 after a number of
consecutive occurrences of RDI as determined by the value in TMUX_CNTDK2[3:0]. Once set, RDI-L will be
cleared after a number of consecutive frames of no RDI as determined by this same value programmed in
TMUX_CNTDK2[3:0]. Any change to TMUX_RLRDIMON, will be reported in TMUX_RLRDIMOND (
Table 82, start-
ing on page79
) and the interrupt can be masked using TMUX_RLRDIMONM (
Table 86 on page 88
). This continu-
ous N-times detection counter will be reset to 0 upon the transition of the framer into the out-of-frame state.
17.5.11 M1 REI-L Detect
One byte (M1) is allocated for use as a line remote error indication function (REI-L). For STS-3/STM-1 signals, all
eight bits of the M1 byte are allocated for REI-L information. The REI-L value reflects the error count detected by
the line terminating equipment (LTE) (using the line BIP-8 code) back to its peer LTE. For STS-3/STM-1 signals, the
value of the error count can be up to 24. A value of 25 and above will be interpreted as no errors. If
TMUX_R_M1_BIT7 (
Table 96 on pag e96
) is 1, then the most significant bit of the byte is ignored.
The TMUX allows access to the accumulated M1-REI errored bit count from the M1 byte via TMUX_M1ECNT[17:0]
(
Table 126 on page 119
). The counter will count in bit or block mode, depending upon the value of
TMUX_BITBLKM1 (
Table 94 on page94
). At the selected performance monitor (PM) interval, the value of the inter-
nal running raw counter is placed into a holding register, TMUX_M1ECNT[17:0], and then cleared. Depending on
the value of SMPR_SAT_ROLLOVER (
Table 67 on pag e68
) in the microprocessor interface, the internal counter
will either roll over or saturate at its maximum value until cleared.
17.5.12 Sync Status Monitor
The S1 byte is allocated for synchronization status. S1 bits [7:4] are used to convey a 4-bit code of which only six
patterns are defined with the remaining codes reserved for quality levels defined by individual administrations.
The S1 byte can be monitored in two modes: (1) as an entire 8-bit word or (2) as one 4-bit nibble (bits [7:4]), as pro-
grammed by TMUX_S1MODE4 (
Table 95 on page 95
).
I
TMUX_S1MODE4 = 0 the associated state, delta, and mask registers are TMUX_RS1MON[7:0] (
Table 103 on
page 100
), TMUX_RS1MOND (
Table 82, starting on page79
), and TMUX_RS1MONM (
Table 86 on page 88
),
respectively.
I
TMUX_S1MODE4 = 1 the associated state, delta, and mask registers are TMUX_RS1MON[7:4],
TMUX_RS1MOND, and TMUX_RS1MONM.
A new value will be detected after a programmed number of consecutive occurrences of a consistent new value in
the incoming S1 byte as determine by the value in TMUX_CNTDS1[3:0] (
Table 98 on page98
). A maskable event,
TMUX_RS1BABE (
Table 82, starting on page79
), is set if a programmed number of consecutive frames pass with-
out a validated message occurring as determined by the value in TMUX_CNTDS1FRAME[3:0] (
Table 98
).
In 8-bit mode, the entire value is monitored for an inconsistent value, while in 4-bit mode, only the most significant
nibble is monitored for an inconsistent value. This continuous N-times detection counter will be reset to 0 upon the
transition of the framer into the out-of-frame state.
17.5.13 Receive Transport Overhead Access Channel (RTOAC)
A transport overhead access channel (TOAC) is provided on-chip to drop the transport overhead (TOH) portion of
the incoming SDH or SONET frame. The TOAC channel supports three modes of operation based on the configu-
ration of TMUX_RTOAC_D13MODE and TMUX_RTOAC_D412MODE (
Table 117 on page113
).