
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Preliminary Data Sheet
May 2001
8 TMUX Registers
(continued)
114
Agere Systems Inc.
0x4004A
8
TMUX_TTOAC_D13MODE
Transmit TOAC DCC1 to DCC3 Only Mode.
When 1, causes DCC1 to DCC3 in the outgoing
frame to be inserted from the TTOAC channel. The
TTOAC clock rate is 260 kHz. If this control bit is a
logic 0 and TMUX_TTOAC_D13MODE is a logic
zero, then the transmit TOAC channel is in full
access mode.
Transmit TOAC Available Byte Control.
When 1,
causes the incoming TOAC values for undefined
bytes (bold-faced bytes in
Table 523
) to be inserted
into the outgoing STS-3/STM-1 frame. Otherwise,
their values depend on SMPR_OH_DEFLT
(
Table 67
).
Transmit TOAC S1 Byte Control.
When 1, causes
the incoming TOAC S1 value to be inserted into the
S1 byte of the outgoing STS-3/STM-1 frame if the
TMUX_THSS1INS (
Table 107
) control bit is deas-
serted. If the S1 is not inserted from register control
or from the transmit TOAC channel, then its value
depends on SMPR_OH_DEFLT.
Transmit TOAC F1 Byte Control.
When 1, causes
the incoming TOAC F1 value to be inserted into the
F1 byte of the outgoing STS-3/STM-1 frame if the
TMUX_THSF1INS (
Table 107
) control bit is desas-
serted. If the F1 is not inserted from register control
or from the transmit TOAC channel, then its value
depends on SMPR_OH_DEFLT.
Transmit TOAC E1 Byte Control.
When 1, causes
the incoming TOAC E1 value to be inserted into the
E1 byte of the outgoing STS-3/STM-1 frame. Other-
wise, the E1 value depends on SMPR_OH_DEFLT.
Transmit TOAC E1 Byte Control.
When 1, causes
the incoming TOAC E1 value to be inserted into the
E1 byte of the outgoing STS-3/STM-1 frame. Other-
wise, the E1 value depends on SMPR_OH_DEFLT.
Transmit TOAC D4 to D12 Byte Control.
When 1,
causes the TTOAC values to be inserted into the D4
to D12 bytes of the outgoing frame. If this control bit
is a logic zero, then the outgoing D4 to D12 values
depend on SMPR_OH_DEFLT.
Transmit TOAC D1 to D3 Byte Control.
When 1,
causes the TTOAC values to be inserted into the D1
to D3 bytes of the outgoing frame. If this control bit is
a logic zero, then the outgoing D1 to D3 values
depend on SMPR_OH_DEFLT.
Transmit TOAC Odd or Even Parity Monitor.
When
1, forces the input TOAC parity checker to check for
odd parity; otherwise, even parity is checked on the
transmit TOAC channel.
0
7
TMUX_TTOAC_AVAIL
0
6
TMUX_TTOAC_S1
0
5
TMUX_TTOAC_F1
0
4
TMUX_TTOAC_E2
0
3
TMUX_TTOAC_E1
0
2
TMUX_TTOAC_D4TO12
0
1
TMUX_TTOAC_D1TO3
0
0
TMUX_TTOAC_OEPMON
0
Table 117. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W)
(continued)
Address
Bit
Name
Function
Reset
Default