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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 95/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
6. INSTRUCTION SET
This section describes the Intel386 DX instruction
set. A table lists all instructions along with instruction
encoding diagrams and clock counts. Further details
of the instruction encoding are then provided in the
following sections, which completely describe the
encoding structure and the definition of all fields oc-
curring within Intel386 DX instructions.
6.1 Intel386
TM
DX INSTRUCTION
ENCODING AND CLOCK COUNT
SUMMARY
To calculate elapsed time for an instruction, multiply
the instruction clock count, as listed in Table 6-1
below, by the processor clock period (e.g. 50 ns for
a 20 MHz Intel386 DX, 40 ns for a 25 MHz Intel386
DX, and 30 ns for a 33 MHz Intel386 DX).
For more detailed information on the encodings of
instructions refer to section 6.2 Instruction Encod-
ings. Section 6.2 explains the general structure of
instruction encodings, and defines exactly the en-
codings of all fields contained within the instruction.
Instruction Clock Count Assumptions
1. The instruction has been prefetched, decoded,
and is ready for execution.
2. Bus cycles do not require wait states.
3. There are no local bus HOLD requests delaying
processor access to the bus.
4. No exceptions are detected during instruction ex-
ecution.
5. If an effective address is calculated, it does not
use two general register components. One regis-
ter, scaling and displacement can be used within
the clock counts shown. However, if the effective
address calculation uses two general register
components, add 1 clock to the clock count
shown.
Instruction Clock Count Notation
1. If two clock counts are given, the smaller refers to
a register operand and the larger refers to a mem-
ory operand.
2. n
e
number of times repeated.
3. m
e
number of components in the next instruc-
tion executed, where the entire displacement (if
any) counts as one component, the entire imme-
diate data (if any) counts as one component, and
each of the
other
bytes of the instruction and pre-
fix(es) each count as one component.
Wait States
Add 1 clock per wait state to instruction execution
for each data access.
95
相關PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內部數(shù)據(jù)總線和24位內部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學協(xié)處理器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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