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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 39/139頁 |
| 文件大小： | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
Code and data segments have several descriptor
fields in common. The accessed
A
bit is set whenev-
er the processor accesses a descriptor. The
A
bit is
used by operating systems to keep usage statistics
on a given segment. The
G
bit, or granularity bit,
specifies if a segment length is byte-granular or
page-granular. Intel386 DX segments can be one
megabyte long with byte granularity (G
e
0) or four
gigabytes with page granularity (G
e
1), (i.e., 2
20
pages each page is 4K bytes in length). The granu-
larity is totally unrelated to paging. An Intel386 DX
system can consist of segments with byte granulari-
ty, and page granularity, whether or not paging is
enabled.
The executable
E
bit tells if a segment is a code or
data segment. A code segment (E
e
1, S
e
1) may be
execute-only or execute/read as determined by the
Read
R
bit. Code segments are execute only if
R
e
0, and execute/read if R
e
1. Code segments
may never be written into.
NOTE:
Code segments may be modified via aliases. Alias-
es are writeable data segments which occupy the
same range of linear address space as the code
segment.
The
D
bit indicates the default length for operands
and effective addresses. If D
e
1 then 32-bit oper-
ands and 32-bit addressing modes are assumed. If
D
e
0 then 16-bit operands and 16-bit addressing
modes are assumed. Therefore all existing 80286
code segments will execute on the Intel386 DX as-
suming the D bit is set 0.
Another attribute of code segments is determined by
the conforming
C
bit. Conforming segments, C
e
1,
can be executed and shared by programs at differ-
ent privilege levels. (See section 4.4
Protection
.)
Segments identified as data segments (E
e
0, S
e
1)
are used for two types of Intel386 DX segments:
stack and data segments. The expansion direction
(ED)
bit specifies if a segment expands downward
(stack) or upward (data). If a segment is a stack seg-
ment all offsets must be greater than the segment
limit. On a data segment all offsets must be less
than or equal to the limit. In other words, stack seg-
ments start at the base linear address plus the maxi-
mum segment limit and grow down to the base linear
address plus the limit. On the other hand, data seg-
ments start at the base linear address and expand to
the base linear address plus limit.
The write
W
bit controls the ability to write into a
segment. Data segments are read-only if W
e
0. The
stack segment must have W
e
1.
The
B
bit controls the size of the stack pointer regis-
ter. If B
e
1, then PUSHes, POPs, and CALLs all use
the 32-bit ESP register for stack references and as-
sume an upper limit of FFFFFFFFH. If B
e
0, stack
instructions all use the 16-bit SP register and as-
sume an upper limit of FFFFH.
4.3.4.3 SYSTEM DESCRIPTOR FORMATS
System segments describe information about oper-
ating system tables, tasks, and gates. Figure 4-7
shows the general format of system segment de-
scriptors, and the various types of system segments.
Intel386 DX system descriptors contain a 32-bit
base linear address and a 20-bit segment limit.
80286 system descriptors have a 24-bit base ad-
dress and a 16-bit segment limit. 80286 system de-
scriptors are identified by the upper 16 bits being all
zero.
31
16
0
SEGMENT BASE 15 . . . 0
SEGMENT LIMIT 15 . . . 0
0
BASE 31 . . . 24
G
0
0
0
LIMIT
19 . . . 16
P
DPL
0
TYPE
BASE
23 . . . 16
a
4
Type
Defines
0
1
2
3
4
5
6
7
Invalid
Available 80286 TSS
LDT
Busy 80286 TSS
80286 Call Gate
Task Gate (for 80286 or Intel386
TM
DX Task)
80286 Interrupt Gate
80286 Trap Gate
Type
Defines
8
9
A
B
C
D
E
F
Invalid
Available Intel386
TM
DX TSS
Undefined (Intel Reserved)
Busy Intel386
TM
DX TSS
Intel386
TM
DX Call Gate
Undefined (Intel Reserved)
Intel386
TM
DX Interrupt Gate
Intel386
TM
DX Trap Gate
NOTE:
In a maximum-size segment (ie. a segment with G
e
1 and segment limit 19...0
e
FFFFFH), the lowest 12 bits of the
segment base should be zero (ie. segment base 11...000
e
000H).
Figure 4-7. System Segments Descriptors
39
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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