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參數資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數： | 23/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
2.7.3 Segment Register Usage
The main data structure used to organize memory is
the segment. On the Intel386 DX, segments are vari-
able sized blocks of linear addresses which have
certain attributes associated with them. There are
two main types of segments: code and data, the
segments are of variable size and can be as small
as 1 byte or as large as 4 gigabytes (2
32
bytes).
In order to provide compact instruction encoding,
and increase processor performance, instructions
do not need to explicitly specify which segment reg-
ister is used. A default segment register is automati-
cally chosen according to the rules of Table 2-4
(Segment Register Selection Rules). In general, data
references use the selector contained in the DS reg-
ister; Stack references use the SS register and In-
struction fetches use the CS register. The contents
of the Instruction Pointer provides the offset. Special
segment override prefixes allow the explicit use of a
given segment register, and override the implicit
rules listed in Table 2-4. The override prefixes also
allow the use of the ES, FS and GS segment regis-
ters.
There are no restrictions regarding the overlapping
of the base addresses of any segments. Thus, all 6
segments could have the base address set to zero
and create a system with a four gigabyte linear ad-
dress space. This creates a system where the virtual
address space is the same as the linear address
space. Further details of segmentation are dis-
cussed in section 4.1.
2.8 I/O SPACE
The Intel386 DX has two distinct physical address
spaces: Memory and I/O. Generally, peripherals are
placed in I/O space although the Intel386 DX also
supports memory-mapped peripherals. The I/O
space consists of 64K bytes, it can be divided into
64K 8-bit ports, 32K 16-bit ports, or 16K 32-bit ports,
or any combination of ports which add up to less
than 64K bytes. The 64K I/O address space refers
to physical memory rather than linear address since
I/O instructions do not go through the segmentation
or paging hardware. The M/IO
Y
pin acts as an addi-
tional address line thus allowing the system designer
to easily determine which address space the proces-
sor is accessing.
Table 2-4. Segment Register Selection Rules
Type of
Implied (Default)
Segment Use
Segment Override
Prefixes Possible
Memory Reference
Code Fetch
CS
None
Destination of PUSH, PUSHF, INT,
CALL, PUSHA Instructions
SS
None
Source of POP, POPA, POPF,
IRET, RET instructions
SS
None
Destination of STOS, MOVS, REP
STOS, REP MOVS Instructions
(DI is Base Register)
ES
None
Other Data References, with
Effective Address Using Base
Register of:
[
EAX
]
[
EBX
]
[
ECX
]
[
EDX
]
[
ESI
]
[
EDI
]
[
EBP
]
[
ESP
]
DS
DS
DS
DS
DS
DS
SS
SS
DS,CS,SS,ES,FS,GS
DS,CS,SS,ES,FS,GS
DS,CS,SS,ES,FS,GS
DS,CS,SS,ES,FS,GS
DS,CS,SS,ES,FS,GS
DS,CS,SS,ES,FS,GS
DS,CS,SS,ES,FS,GS
DS,CS,SS,ES,FS,GS
23
相關PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內部數據總線和24位內部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數學協(xié)處理器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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