參數(shù)資料
型號: intel386 DX
廠商: Intel Corp.
英文描述: 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述: 32位CHMOS微處理器集成內(nèi)存管理(32位CHMOS微處理器帶集成存儲管理)
文件頁數(shù): 22/139頁
文件大?。?/td> 1587K
代理商: INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
2.7 MEMORY ORGANIZATION
2.7.1 Introduction
Memory on the Intel386 DX is divided up into 8-bit
quantities (bytes), 16-bit quantities (words), and
32-bit quantities (dwords). Words are stored in two
consecutive bytes in memory with the low-order byte
at the lowest address, the high order byte at the high
address. Dwords are stored in four consecutive
bytes in memory with the low-order byte at the low-
est address, the high-order byte at the highest ad-
dress. The address of a word or dword is the byte
address of the low-order byte.
In addition to these basic data types, the Intel386
DX supports two larger units of memory: pages and
segments. Memory can be divided up into one or
more variable length segments, which can be
swapped to disk or shared between programs. Mem-
ory can also be organized into one or more 4K byte
pages. Finally, both segmentation and paging can
be combined, gaining the advantages of both sys-
tems. The Intel386 DX supports both pages and
segments in order to provide maximum flexibility to
the system designer. Segmentation and paging are
complementary. Segmentation is useful for organiz-
ing memory in logical modules, and as such is a tool
for the application programmer, while pages are use-
ful for the system programmer for managing the
physical memory of a system.
2.7.2 Address Spaces
The Intel386 DX has three distinct address spaces:
logical, linear,
and
physical
. A
logical
address
(also known as a
virtual
address) consists of a se-
lector and an offset. A selector is the contents of a
segment register. An offset is formed by summing all
of the addressing components (BASE, INDEX, DIS-
PLACEMENT) discussed in section 2.5.3
Memory
Addressing Modes
into an effective address. Since
each task on Intel386 DX has a maximum of 16K
(2
14
b
1) selectors, and offsets can be 4 gigabytes,
(2
32
bits) this gives a total of 2
46
bits or 64 terabytes
of
logical
address space per task. The programmer
sees this virtual address space.
The segmentation unit translates the
logical
ad-
dress space into a 32-bit
linear
address space. If the
paging unit is not enabled then the 32-bit
linear
ad-
dress corresponds to the
physical
address. The
paging unit translates the
linear
address space into
the
physical
address space. The
physical address
is what appears on the address pins.
The primary difference between Real Mode and Pro-
tected Mode is how the segmentation unit performs
the translation of the
logical
address into the
linear
address. In Real Mode, the segmentation unit shifts
the selector left four bits and adds the result to the
offset to form the
linear
address. While in Protected
Mode every selector has a
linear
base address as-
sociated with it. The
linear base
address is stored in
one of two operating system tables (i.e. the Local
Descriptor Table or Global Descriptor Table). The
selector’s
linear base
address is added to the offset
to form the final
linear
address.
Figure 2-11 shows the relationship between the vari-
ous address spaces.
231630–53
Figure 2-11. Address Translation
22
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