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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 66/139頁 |
| 文件大小： | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
5.2.8.4 COPROCESSOR ERROR (ERROR
Y
)
This input signal indicates that the previous coproc-
essor instruction generated a coprocessor error of a
type not masked by the coprocessor’s control regis-
ter. This input is automatically sampled by the In-
tel386 DX when a coprocessor instruction is en-
countered, and if asserted, the Intel386 DX gener-
ates exception 16 to access the error-handling soft-
ware.
Several coprocessor instructions, generally those
which clear the numeric error flags in the coproces-
sor or save coprocessor state, do execute without
the Intel386 DX generating exception 16 even if ER-
ROR
Y
is asserted. These instructions are FNINIT,
FNCLEX, FSTSW, FSTSWAX, FSTCW, FSTENV,
FSAVE, FESTENV and FESAVE.
ERROR
Y
is level-sensitive and is allowed to be
asynchronous to the CLK2 signal.
5.2.9 Interrupt Signals (INTR, NMI,
RESET)
5.2.9.1 INTRODUCTION
The following descriptions cover inputs that can in-
terrupt or suspend execution of the processor’s cur-
rent instruction stream.
5.2.9.2 MASKABLE INTERRUPT REQUEST (INTR)
When asserted, this input indicates a request for in-
terrupt service, which can be masked by the Intel386
DX Flag Register IF bit. When the Intel386 DX re-
sponds to the INTR input, it performs two interrupt
acknowledge bus cycles, and at the end of the sec-
ond, latches an 8-bit interrupt vector on D0–D7 to
identify the source of the interrupt.
INTR is level-sensitive and is allowed to be asyn-
chronous to the CLK2 signal. To assure recognition
of an INTR request, INTR should remain asserted
until the first interrupt acknowledge bus cycle be-
gins.
5.2.9.3 NON-MASKABLE INTERRUPT REQUEST
(NMI)
This input indicates a request for interrupt service,
which cannot be masked by software. The non-
maskable interrupt request is always processed ac-
cording to the pointer or gate in slot 2 of the interrupt
table. Because of the fixed NMI slot assignment, no
interrupt acknowledge cycles are perfomed when
processing NMI.
NMI is rising edge-sensitive and is allowed to be
asynchronous to the CLK2 signal. To assure recog-
nition of NMI, it must be negated for at least eight
CLK2 periods, and then be asserted for at least
eight CLK2 periods.
Once NMI processing has begun, no additional
NMI’s are processed until after the next IRET in-
struction, which is typically the end of the NMI serv-
ice routine. If NMI is re-asserted prior to that time,
however, one rising edge on NMI will be remem-
bered for processing after executing the next IRET
instruction.
5.2.9.4 RESET (RESET)
This input signal suspends any operation in progress
and places the Intel386 DX in a known reset state.
The Intel386 DX is reset by asserting RESET for 15
or more CLK2 periods (80 or more CLK2 periods
before requesting self test). When RESET is assert-
ed, all other input pins are ignored, and all other bus
pins are driven to an idle bus state as shown in Ta-
ble 5-3. If RESET and HOLD are both asserted at a
point in time, RESET takes priority even if the In-
tel386 DX was in a Hold Acknowledge state prior to
RESET asserted.
RESET is level-sensitive and must be synchronous
to the CLK2 signal. If desired, the phase of the inter-
nal processor clock, and the entire Intel386 DX state
can be completely synchronized to external circuitry
by ensuring the RESET signal falling edge meets its
applicable setup and hold times, t
25
and t
26
.
Table 5-3. Pin State (Bus Idle) During Reset
Pin Name
ADS
Y
D0–D31
BE0
Y
–BE3
Y
A2–A31
W/R
Y
D/C
Y
M/IO
Y
LOCK
Y
HLDA
Signal Level During Reset
High
High Impedance
Low
High
Low
High
Low
High
Low
66
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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