參數(shù)資料
型號: intel386 DX
廠商: Intel Corp.
英文描述: 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述: 32位CHMOS微處理器集成內(nèi)存管理(32位CHMOS微處理器帶集成存儲管理)
文件頁數(shù): 117/139頁
文件大?。?/td> 1587K
代理商: INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
231630–84
Figure 7-1. Processor Module Dimensions
7. DESIGNING FOR ICE
TM
-Intel386
DX EMULATOR USE
The Intel386 DX in-circuit emulator products are
ICE-Intel386 DX 25 MHz or 33 MHz (both referred to
as ICE-Intel386 DX emulator). The ICE-Intel386 DX
emulator probe module has several electrical and
mechanical characteristics that should be taken into
consideration when designing the hardware.
Capacitive loading:
The ICE-Intel386 DX emulator
adds up to 25 pF to each line.
Drive requirement:
The ICE-Intel386 DX emulator
adds one standard TTL load on the CLK2 line, up to
one advanced low-power Schottky TTL load per
control signal line, and one advanced low-power
Schottky TTL load per address, byte enable, and
data line. These loads are within the probe module
and are driven by the probe’s Intel386 DX compo-
nent, which has standard drive and loading capabili-
ty listed in the A.C. and D.C. Specification Tables in
Sections 9.4 and 9.5.
Power requirement:
For noise immunity the ICE-In-
tel386 DX emulator probe is powered by the user
system. This high-speed probe circuitry draws up to
1.5A plus the maximum I
CC
from the user Intel386
DX component socket.
Intel386 DX location and orientation:
The ICE-In-
tel386 DX processor module, target-adaptor cable
(which does not exist for the ICE-Intel386 DX
33 MHz emulator), and the isolation board used for
extra electrical buffering of the emulator initially, re-
quire clearance as illustrated in Figures 7-1 and 7-2.
Interface Board and CLK2 speed reduction:
When the ICE-Intel386 DX emulator probe is first
attached to an unverified user system, the interface
board helps the ICE-Intel386 DX emulator function
in user systems with bus faults (shorted signals,
etc.). After electrical verification it may be removed.
Only when the interface board is installed, the user
system must have a reduced CLK2 frequency of
25 MHz maximum.
Cache coherence:
The ICE-Intel386 DX emulator
loads user memory by performing Intel386 DX com-
ponent write cycles. Note that if the user system is
not designed to update or invalidate its cache (if it
has a cache) upon processor writes to memory, the
cache could contain stale instruction code and/or
data. For best use of the ICE-Intel386 DX emulator,
the user should consider designing the cache (if any)
to update itself automatically when processor writes
occur, or find another method of maintaining cache
data coherence with main user memory.
117
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