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參數(shù)資料
| 型號(hào)： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理） |
| 文件頁數(shù)： | 18/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
2.5 ADDRESSING MODES
2.5.1 Addressing Modes Overview
The Intel386 DX provides a total of 11 addressing
modes for instructions to specify operands. The ad-
dressing modes are optimized to allow the efficient
execution of high level languages such as C and
FORTRAN, and they cover the vast majority of data
references needed by high-level languages.
2.5.2 Register and Immediate Modes
Two of the addressing modes provide for instruc-
tions that operate on register or immediate oper-
ands:
Register Operand Mode:
The operand is located
in one of the 8-, 16- or 32-bit general registers.
Immediate Operand Mode:
The operand is in-
cluded in the instruction as part of the opcode.
2.5.3 32-Bit Memory Addressing
Modes
The remaining 9 modes provide a mechanism for
specifying the effective address of an operand. The
linear address consists of two components: the seg-
ment base address and an effective address. The
effective address is calculated by using combina-
tions of the following four address elements:
DISPLACEMENT:
An 8-, or 32-bit immediate value,
following the instruction.
BASE:
The contents of any general purpose regis-
ter. The base registers are generally used by compil-
ers to point to the start of the local variable area.
INDEX:
The contents of any general purpose regis-
ter except for ESP. The index registers are used to
access the elements of an array, or a string of char-
acters.
SCALE:
The index register’s value can be multiplied
by a scale factor, either 1, 2, 4 or 8. Scaled index
mode is especially useful for accessing arrays or
structures.
Combinations of these 4 components make up the 9
additional addressing modes. There is no perform-
ance penalty for using any of these addressing com-
binations, since the effective address calculation is
pipelined with the execution of other instructions.
The one exception is the simultaneous use of Base
and Index components which requires one addition-
al clock.
As shown in Figure 2-9, the effective address (EA) of
an operand is calculated according to the following
formula.
EA
e
Base Reg
a
(Index Reg
*
Scaling)
a
Displacement
Direct Mode: The operand’s offset is contained as
part of the instruction as an 8-, 16- or 32-bit dis-
placement.
EXAMPLE: INC Word PTR
[
500
]
Register Indirect Mode: A BASE register contains
the address of the operand.
EXAMPLE: MOV
[
ECX
]
, EDX
Based Mode: A BASE register’s contents is added
to a DISPLACEMENT to form the operands offset.
EXAMPLE: MOV ECX,
[
EAX
a
24
]
Index Mode: An INDEX register’s contents is added
to a DISPLACEMENT to form the operands offset.
EXAMPLE: ADD EAX, TABLE
[
ESI
]
Scaled Index Mode: An INDEX register’s contents is
multiplied by a scaling factor which is added to a
DISPLACEMENT to form the operands offset.
EXAMPLE: IMUL EBX, TABLE
[
ESI
*
4
]
,7
Based Index Mode: The contents of a BASE register
is added to the contents of an INDEX register to
form the effective address of an operand.
EXAMPLE: MOV EAX,
[
ESI
] [
EBX
]
Based Scaled Index Mode: The contents of an IN-
DEX register is multiplied by a SCALING factor and
the result is added to the contents of a BASE regis-
ter to obtain the operands offset.
EXAMPLE: MOV ECX,
[
EDX
*
8
] [
EAX
]
Based Index Mode with Displacement: The contents
of an INDEX Register and a BASE register’s con-
tents and a DISPLACEMENT are all summed to-
gether to form the operand offset.
EXAMPLE: ADD EDX,
[
ESI
] [
EBP
a
00FFFFF0H
]
Based Scaled Index Mode with Displacement: The
contents of an INDEX register are multiplied by a
SCALING factor, the result is added to the contents
of a BASE register and a DISPLACEMENT to form
the operand’s offset.
EXAMPLE:
MOV
EAX,
[
EBP
a
80
]
LOCALTABLE
[
EDI
*
4
]
18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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