參數(shù)資料
型號： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理）
文件頁數(shù)： 54/139頁
文件大小： 1587K
代理商： INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
31
12
11
10
9
8
7
6
5
4
3
2
1
0
OS
RESERVED
U
D
S
R
D
W
PAGE FRAME ADDRESS 31..12
0
0
D
A
0
0
P
Figure 4-21. Page Table Entry (Points to Page)
4.5.2.4 PAGE TABLES
Each Page Table is 4K bytes and holds up to 1024
Page Table Entries. Page Table Entries contain the
starting address of the page frame and statistical
information about the page (see Figure 4-21). Ad-
dress bits A12–A21 are used as an index to select
one of the 1024 Page Table Entries. The 20 upper-
bit page frame address is concatenated with the
lower 12 bits of the linear address to form the physi-
cal address. Page tables can be shared between
tasks and swapped to disks.
4.5.2.5 PAGE DIRECTORY/TABLE ENTRIES
The lower 12 bits of the Page Table Entries and
Page Directory Entries contain statistical information
about pages and page tables respectively. The
P
(Present) bit 0 indicates if a Page Directory or Page
Table entry can be used in address translation. If
P
e
1 the entry can be used for address translation;
if P
e
0 the entry can not be used for translation.
Note that the present bit of the page table entry that
points to the page where code is currently being ex-
ecuted should always be set. Code that marks its
own page not present should not be written. All of
the other bits are available for use by the software.
For example the remaining 31 bits could be used to
indicate where on the disk the page is stored.
The
A
(Accessed) bit 5, is set by the Intel386 DX for
both types of entries before a read or write access
occurs to an address covered by the entry. The
D
(Dirty) bit 6 is set to 1 before a write to an address
covered by that page table entry occurs. The D bit is
undefined for Page Directory Entries. When the P, A
and D bits are updated by the Intel386 DX, the proc-
essor generates a Read-Modify-Write cycle which
locks the bus and prevents conflicts with other proc-
essors or perpherials. Software which modifies
these bits should use the LOCK prefix to ensure the
integrity of the page tables in multi-master systems.
The 3 bits marked
OS Reserved
in Figure 4-20 and
Figure 4-21 (bits 9–11) are software definable. OSs
are free to use these bits for whatever purpose they
wish. An example use of the
OS Reserved
bits
would be to store information about page aging. By
keeping track of how long a page has been in mem-
ory since being accessed, an operating system can
implement a page replacement algorithm like Least
Recently Used.
The (User/Supervisor) U/S bit 2 and the (Read/
Write) R/W bit 1 are used to provide protection attri-
butes for individual pages.
4.5.3 Page Level Protection
(R/W, U/S Bits)
The Intel386 DX provides a set of protection attri-
butes for paging systems. The paging mechanism
distinguishes between two levels of protection: User
which corresponds to level 3 of the segmentation
based protection, and supervisor which encompass-
es all of the other protection levels (0, 1, 2). Pro-
grams executing at Level 0, 1 or 2 bypass the page
protection, although segmentation based protection
is still enforced by the hardware.
The U/S and R/W bits are used to provide
User/Supervisor and Read/Write protection for indi-
vidual pages or for all pages covered by a Page Ta-
ble Directory Entry. The U/S and R/W bits in the first
level Page Directory Table apply to all pages de-
scribed by the page table pointed to by that directory
entry. The U/S and R/W bits in the second level
Page Table Entry apply only to the page described
by that entry. The U/S and R/W bits for a given
page are obtained by taking the most restrictive of
the U/S and R/W from the Page Directory Table
Entries and the Page Table Entries and using these
bits to address the page.
Example: If the U/S and R/W bits for the Page Di-
rectory entry were 10 and the U/S and R/W bits for
the Page Table Entry were 01, the access rights for
the page would be 01, the numerically smaller of the
two. Table 4-4 shows the affect of the U/S and R/W
bits on accessing memory.
Table 4-4. Protection Provided by R/W and U/S
U/S
R/W
Permitted
Level 3
Permitted Access
Levels 0, 1, or 2
0
0
1
1
0
1
0
1
None
None
Read-Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
However a given segment can be easily made read-
only for level 0, 1, or 2 via the use of segmented
protection mechanisms. (Section 4.4
Protection
).
54
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