參數(shù)資料
型號(hào)： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理）
文件頁(yè)數(shù)： 34/139頁(yè)
文件大?。?/td> 1587K
代理商： INTEL386 DX
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)當(dāng)前第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)
Intel386
TM
DX MICROPROCESSOR
Segments may be overlapped in Real Mode. Thus, if
a particular segment does not use all 64K bytes an-
other segment can be overlayed on top of the un-
used portion of the previous segment. This allows
the programmer to minimize the amount of physical
memory needed for a program.
3.3 RESERVED LOCATIONS
There are two fixed areas in memory which are re-
served in Real address mode: system initialization
area and the interrupt table area. Locations 00000H
through 003FFH are reserved for interrupt vectors.
Each one of the 256 possible interrupts has a 4-byte
jump vector reserved for it. Locations FFFFFFF0H
through FFFFFFFFH are reserved for system initiali-
zation.
3.4 INTERRUPTS
Many of the exceptions shown in Table 2-5 and dis-
cussed in section 2.9 are not applicable to Real
Mode operation, in particular exceptions 10, 11, 14,
will not happen in Real Mode. Other exceptions
have slightly different meanings in Real Mode; Table
3-1 identifies these exceptions.
3.5 SHUTDOWN AND HALT
The HLT instruction stops program execution and
prevents the processor from using the local bus until
restarted. Either NMI, INTR with interrupts enabled
(IF
e
1), or RESET will force the Intel386 DX out of
halt. If interrupted, the saved CS:IP will point to the
next instruction after the HLT.
Shutdown will occur when a severe error is detected
that prevents further processing. In Real Mode,
shutdown can occur under two conditions:
An interrupt or an exception occur (Exceptions 8
or 13) and the interrupt vector is larger than the
Interrupt Descriptor Table (i.e. There is not an in-
terrupt handler for the interrupt).
A CALL, INT or PUSH instruction attempts to wrap
around the stack segment when SP is not even.
(e.g. pushing a value on the stack when SP
e
0001 resulting in a stack segment greater than
FFFFH)
An NMI input can bring the processor out of shut-
down if the Interrupt Descriptor Table limit is large
enough to contain the NMI interrupt vector (at least
0017H) and the stack has enough room to contain
the vector and flag information (i.e. SP is greater
than 0005H). Otherwise shutdown can only be exit-
ed via the RESET input.
4. PROTECTED MODE
ARCHITECTURE
4.1 INTRODUCTION
The complete capabilities of the Intel386 DX are un-
locked when the processor operates in Protected
Virtual Address Mode (Protected Mode). Protected
Mode vastly increases the linear address space to
four gigabytes (2
32
bytes) and allows the running of
virtual memory programs of almost unlimited size
(64 terabytes or 2
46
bytes). In addition Protected
Mode allows the Intel386 DX to run all of the existing
8086 and 80286 software, while providing a sophisti-
cated memory management and a hardware-assist-
ed protection mechanism. Protected Mode allows
the use of additional instructions especially opti-
mized for supporting multitasking operating systems.
The base architecture of the Intel386 DX remains
the same, the registers, instructions, and addressing
modes described in the previous sections are re-
tained. The main difference between Protected
Mode, and Real Mode from a programmer’s view is
the increased address space, and a different ad-
dressing mechanism.
Table 3-1
Function
Interrupt
Number
Related
Instructions
Return
Address Location
Interrupt table limit too small
8
INT Vector is not
within table limit
Before
Instruction
CS, DS, ES, FS, GS
Segment overrun exception
13
Word memory reference
beyond offset
e
FFFFH.
An attempt to execute
past the end of CS segment.
Before
Instruction
SS Segment overrun exception
12
Stack Reference
beyond offset
e
FFFFH
Before
Instruction
34
相關(guān)PDF資料
PDF描述
Intel386 EX Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器)
INTEL386 SXSA 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器)
intel386 SX 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器)
INTEL386 Intel386 EX Embedded Microprocessor
Intel387 dx DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
INTEL386SX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR
INTEL387 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR
INTEL387DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR
INTEL387SX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR
INTEL387TMDX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*