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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 64/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
Table 5-2. Bus Cycle Definition
M/IO
Y
D/C
Y
W/R
Y
Bus Cycle Type
Locked
Low
Low
Low
INTERRUPT ACKNOWLEDGE
Yes
Low
Low
High
does not occur
D
Low
High
Low
I/O DATA READ
No
Low
High
High
I/O DATA WRITE
No
High
Low
Low
MEMORY CODE READ
No
High
Low
High
HALT:
Address
e
2
(BE0
Y
High
BE1
Y
High
BE2
Y
Low
BE3
Y
High
A2–A31 Low)
SHUTDOWN:
Address
e
0
(BE0
Y
Low
BE1
Y
High
BE2
Y
High
BE3
Y
High
A2–A31 Low)
No
High
High
Low
MEMORY DATA READ
Some Cycles
High
High
High
MEMORY DATA WRITE
Some Cycles
5.2.6 Bus Control Signals (ADS
Y
,
READY
Y
, NA
Y
, BS16
Y
)
5.2.6.1 INTRODUCTION
The following signals allow the processor to indicate
when a bus cycle has begun, and allow other system
hardware to control address pipelining, data bus
width and bus cycle termination.
5.2.6.2 ADDRESS STATUS (ADS
Y
)
This three-state output indicates that a valid bus cy-
cle definition, and address (W/R
Y
, D/C
Y
, M/IO
Y
,
BE0
Y
–BE3
Y
, and A2–A31) is being driven at the
Intel386 DX pins. It is asserted during T1 and T2P
bus states (see
5.4.3.2 Non-pipelined Address
and
5.4.3.4 Pipelined Address
for additional information
on bus states).
5.2.6.3 TRANSFER ACKNOWLEDGE (READY
Y
)
This input indicates the current bus cycle is com-
plete, and the active bytes indicated by BE0
Y
–
BE3
Y
and BS16
Y
are accepted or provided. When
READY
Y
is sampled asserted during a read cycle or
interrupt acknowledge cycle, the Intel386 DX latches
the input data and terminates the cycle. When
READY
Y
is sampled asserted during a write cycle,
the processor terminates the bus cycle.
READY
Y
is ignored on the first bus state of all bus
cycles, and sampled each bus state thereafter until
asserted. READY
Y
must eventually be asserted to
acknowledge every bus cycle, including Halt Indica-
tion and Shutdown Indication bus cycles. When be-
ing sampled, READY must always meet setup and
hold times t
19
and t
20
for correct operation. See all
sections of
5.4 Bus Functional Description
.
5.2.6.4 NEXT ADDRESS REQUEST (NA
Y
)
This is used to request address pipelining. This input
indicates the system is prepared to accept new val-
ues of BE0
Y
–BE3
Y
, A2–A31, W/R
Y
, D/C
Y
and
M/IO
Y
from the Intel386 DX even if the end of the
current
cycle
is
not
being
READY
Y
. If this input is asserted when sampled,
the next address is driven onto the bus, provided the
next bus request is already pending internally. See
5.4.2 Address Pipelining
and
5.4.3 Read and
Write Cycles
. NA
Y
must always meet setup and
hold times, t
15
and t
16
, for correct operation.
acknowledged
on
5.2.6.5 BUS SIZE 16 (BS16
Y
)
The BS16
Y
feature allows the Intel386 DX to direct-
ly connect to 32-bit and 16-bit data buses. Asserting
this input constrains the current bus cycle to use
only the lower-order half (D0–D15) of the data bus,
corresponding to BE0
Y
and BE1
Y
. Asserting
BS16
Y
has no additional effect if only BE0
Y
and/or
BE1
Y
are asserted in the current cycle. However,
during bus cycles asserting BE2
Y
or BE3
Y
, assert-
ing BS16
Y
will automatically cause the Intel386 DX
to make adjustments for correct transfer of the up-
per bytes(s) using only physical data signals D0–
D15.
If the operand spans both halves of the data bus
and BS16
Y
is asserted, the Intel386 DX will auto-
matically perform another 16-bit bus cycle. BS16
Y
must always meet setup and hold times t
17
and t
18
for correct operation.
64
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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