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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 62/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
231630–1
Figure 5-1. Functional Signal Groups
231630–2
Figure 5-2. CLK2 Signal and Internal Processor Clock
The signal descriptions sometimes refer to AC tim-
ing parameters, such as ‘‘t
25
Reset Setup Time’’ and
‘‘t
26
Reset Hold Time.’’ The values of these parame-
ters can be found in Tables 7-4 and 7-5.
5.2.2 Clock (CLK2)
CLK2 provides the fundamental timing for the In-
tel386 DX. It is divided by two internally to generate
the internal processor clock used for instruction exe-
cution. The internal clock is comprised of two phas-
es, ‘‘phase one’’ and ‘‘phase two.’’ Each CLK2 peri-
od is a phase of the internal clock. Figure 5-2 illus-
trates the relationship. If desired, the phase of the
internal processor clock can be synchronized to a
known phase by ensuring the RESET signal falling
edge meets its applicable setup and hold times, t
25
and t
26
.
5.2.3 Data Bus (D0 through D31)
These three-state bidirectional signals provide the
general purpose data path between the Intel386 DX
and other devices. Data bus inputs and outputs indi-
cate ‘‘1’’ when HIGH. The data bus can transfer data
on 32- and 16-bit buses using a data bus sizing fea-
ture controlled by the BS16
Y
input. See section
5.2.6 Bus Contol
. Data bus reads require that read
data setup and hold times t
21
and t
22
be met for
correct operation. In addition, the Intel386 DX re-
quires that all data bus pins be at a valid logic state
(high or low) at the end of each read cycle, when
READY
Y
is asserted. During any write operation
(and during halt cycles and shutdown cycles), the
Intel386 DX always drives all 32 signals of the data
bus even if the current bus size is 16-bits.
5.2.4 Address Bus (BE0
Y
through
BE3
Y
, A2 through A31)
These three-state outputs provide physical memory
addresses or I/O port addresses. The address bus
is capable of addressing 4 gigabytes of physical
memory space (00000000H through FFFFFFFFH),
and 64 kilobytes of I/O address space (00000000H
through 0000FFFFH) for programmed I/O. I/O
62
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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