參數(shù)資料
型號(hào)： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理）
文件頁(yè)數(shù)： 137/139頁(yè)
文件大小： 1587K
代理商： INTEL386 DX
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Intel386
TM
DX MICROPROCESSOR
10. REVISION HISTORY
This Intel386 DX data sheet, version -005, contains updates and improvements to previous versions. A revi-
sion summary is listed here for your convenience.
The sections significantly revised since version -001 are:
2.9.6
Sequence of exception checking table added.
2.9.7
Instruction restart revised.
2.11.2
TLB testing revised.
2.12
Debugging support revised.
3.1
LOCK prefix restricted to certain instructions.
4.4.3.3
I/O privilege level and I/O permission bitmap added.
Figures 4-15a, 4-15b
I/O permission bitmap added.
4.6.4
Protection and I/O permission bitmap revised.
4.6.6
Entering and leaving virtual 8086 mode through task switches, trap and interrupt
gates, and IRET explained.
5.6
Self-test signature stored in EAX.
5.8
Coprocessor interface description added.
5.8.1
Software testing for coprocessor presence added.
Table 6-3
PGA package thermal characteristics added.
7.
Designing for ICE-Intel386 revised.
Figures 7-8, 7-9, 7-10
ICE-Intel386 clearance requirements added.
6.2.3.4
Encoding of 32-bit address mode with no ‘‘sib’’ byte corrected.
The sections significantly revised since version -002 are:
Table 2-5
Interrupt vector assignments updated.
Figure 4-15a
BitDmapDoffset must be less than or equal to DFFFH.
Intel386 DX outputs remain in their reset state during self-test.
Figure 5-28
5.7
Component and revision identifier history updated.
9.4
20 MHz D.C. specifications added.
9.5
16 MHz A.C. specifications updated. 20 MHz A.C. specifications added.
Table 6-1
Clock counts updated.
The sections significantly revised since version -003 are:
Table 2-6b
Interrupt priorities 2 and 3 interchanged.
2.9.8
Double page faults do not raise double fault exception.
Maximum-sized segments must have segments Base
11..0
e
0.
BS16
Y
timing corrected.
BS16
Y
timing corrected. BS16
Y
must not be asserted once NA
Y
has been
Figure 4-5
5.4.3.4
Figures 5-16, 5-17,
5-19, 5-22
sampled asserted in the current bus cycle.
9.5
16 MHz and 20 MHz A.C. specifications revised. All timing parameters are now
guaranteed at 1.5V test levels. The timing parameters have been adjusted to
remain compatible with previous 0.8V/2.0V specifications.
137
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