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參數(shù)資料
| 型號(hào)： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理） |
| 文件頁(yè)數(shù)： | 78/139頁(yè) |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
Bus States:
T1Dfirst clock of a non-pipelined bus cycle (Intel386 DX drives new address and asserts ADS
Y
)
T2Dsubsequent clocks of a bus cycle when NA
Y
has not been sampled asserted in the current bus cycle
TiD idle state
ThDhold acknowledge state (Intel386 DX asserts HLDA)
The fastest bus cycle consists of two states: T1 and T2.
Four basic bus states describe bus operation when not using pipelined address. These states do include BS16
Y
usage for 32-bit and 16-bit
bus size. If asserting BS16
Y
requires a second 16-bit bus cycle to be performed, it is performed before HOLD asserted is acknowledged.
231630–17
Figure 5-13. Intel386
TM
DX Bus States (not using pipelined address)
When address pipelining is not used, the address
and bus cycle definition remain valid during all wait
states. When wait states are added and you desire
to maintain non-pipelined address timing, it is neces-
sary to negate NA
Y
during each T2 state except the
last one, as shown in Figure 5-12 cycles 2 and 3. If
NA
Y
is sampled asserted during a T2 other than the
last one, the next state would be T2I (for pipelined
address) or T2P (for pipelined address) instead of
another T2 (for non-pipelined address).
When address pipelining is not used, the bus states
and transitions are completely illustrated by Figure
5-13. The bus transitions between four possible
states: T1, T2, Ti, and Th. Bus cycles consist of T1
and T2, with T2 being repeated for wait states. Oth-
erwise, the bus may be idle, in the Ti state, or in hold
acknowledge, the Th state.
When address pipelining is not used, the bus state
diagram is as shown in Figure 5-13. When the bus is
idle it is in state Ti. Bus cycles always begin with T1.
T1 always leads to T2. If a bus cycle is not acknowl-
edged during T2 and NA
Y
is negated, T2 is repeat-
ed. When a cycle is acknowledged during T2, the
following state will be T1 of the next bus cycle if a
bus request is pending internally, or Ti if there is no
bus request pending, or Th if the HOLD input is be-
ing asserted.
The bus state diagram in Figure 5-13 also applies to
the use of BS16
Y
. If the Intel386 DX makes internal
adjustments for 16-bit bus size, the adjustments do
not affect the external bus states. If an additional
16-bit bus cycle is required to complete a transfer on
a 16-bit bus, it also follows the state transitions
shown in Figure 5-13.
Use of pipelined address allows the Intel386 DX to
enter three additional bus states not shown in Figure
5-13. Figure 5-20 in
5.4.3.4 Pipelined Address
is
the complete bus state diagram, including pipelined
address cycles.
78
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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