參數(shù)資料
型號(hào)： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理）
文件頁(yè)數(shù)： 36/139頁(yè)
文件大?。?/td> 1587K
代理商： INTEL386 DX
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Intel386
TM
DX MICROPROCESSOR
4.3 SEGMENTATION
4.3.1 Segmentation Introduction
Segmentation is one method of memory manage-
ment. Segmentation provides the basis for protec-
tion. Segments are used to encapsulate regions of
memory which have common attributes. For exam-
ple, all of the code of a given program could be con-
tained in a segment, or an operating system table
may reside in a segment. All information about a
segment is stored in an 8 byte data structure called
a descriptor. All of the descriptors in a system are
contained in tables recognized by hardware.
4.3.2 Terminology
The following terms are used throughout the discus-
sion of descriptors, privilege levels and protection:
PL:
Privilege LevelDOne of the four hierarchical
privilege levels. Level 0 is the most privileged level
and level 3 is the least privileged. More privileged
levels are numerically smaller than less privileged
levels.
RPL:
Requestor Privilege LevelDThe privilege level
of the original supplier of the selector. RPL is deter-
mined by the
least two
significant bits of a selector.
DPL:
Descriptor Privilege LevelDThis is the least
privileged level at which a task may access that de-
scriptor (and the segment associated with that de-
scriptor). Descriptor Privilege Level is determined by
bits 6:5 in the Access Right Byte of a descriptor.
CPL:
Current Privilege LevelDThe privilege level at
which a task is currently executing, which equals the
privilege level of the code segment being executed.
CPL can also be determined by examining the low-
est 2 bits of the CS register, except for conforming
code segments.
EPL:
Effective Privilege LevelDThe effective privi-
lege level is the least privileged of the RPL and DPL.
Since smaller privilege level
values
indicate greater
privilege, EPL is the numerical maximum of RPL and
DPL.
Task:
One instance of the execution of a program.
Tasks are also referred to as processes.
4.3.3 Descriptor Tables
4.3.3.1 DESCRIPTOR TABLES INTRODUCTION
The descriptor tables define all of the segments
which are used in an Intel386 DX system. There are
three types of tables on the Intel386 DX which hold
descriptors: the Global Descriptor Table, Local De-
scriptor Table, and the Interrupt Descriptor Table. All
of the tables are variable length memory arrays.
They can range in size between 8 bytes and 64K
bytes. Each table can hold up to 8192 8 byte de-
scriptors. The upper 13 bits of a selector are used as
an index into the descriptor table. The tables have
registers associated with them which hold the 32-bit
linear base address, and the 16-bit limit of each ta-
ble.
Each of the tables has a register associated with it
the GDTR, LDTR, and the IDTR (see Figure 4-3).
The LGDT, LLDT, and LIDT instructions, load the
base and limit of the Global, Local, and Interrupt De-
scriptor Tables, respectively, into the appropriate
register. The SGDT, SLDT, and SIDT instructions
store the base and limit values. These tables are
manipulated by the operating system. Therefore, the
load descriptor table instructions are privileged in-
structions.
4.3.3.2 GLOBAL DESCRIPTOR TABLE
The Global Descriptor Table (GDT) contains de-
scriptors which are possibly available to all of the
tasks in a system. The GDT can contain any type of
segment descriptor except for descriptors which are
used for servicing interrupts (i.e. interrupt and trap
descriptors). Every Intel386 DX system contains a
231630–57
Figure 4-3. Descriptor Table Registers
36
相關(guān)PDF資料
PDF描述
Intel386 EX Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器)
INTEL386 SXSA 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器)
intel386 SX 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器)
INTEL386 Intel386 EX Embedded Microprocessor
Intel387 dx DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
INTEL386SX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR
INTEL387 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR
INTEL387DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR
INTEL387SX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR
INTEL387TMDX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR
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