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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 76/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
5.4.3 Read and Write Cycles
5.4.3.1 INTRODUCTION
Data transfers occur as a result of bus cycles, classi-
fied as read or write cycles. During read cycles, data
is transferred from an external device to the proces-
sor. During write cycles data is transferred in the oth-
er direction, from the processor to an external de-
vice.
Two choices of address timing are dynamically se-
lectable: non-pipelined, or pipelined. After a bus idle
state, the processor always uses non-pipelined ad-
dress timing. However, the NA
Y
(Next Address) in-
put may be asserted to select pipelined address
timing for the next bus cycle. When pipelining is se-
lected and the Intel386 DX has a bus request pend-
ing internally, the address and definition of the next
cycle is made available even before the current bus
cycle is acknowledged by READY
Y
. Generally, the
NA
Y
input is sampled each bus cycle to select the
desired address timing for the next bus cycle.
Two choices of physical data bus width are dynami-
cally selectable: 32 bits, or 16 bits. Generally, the
BS16
Y
(Bus Size 16) input is sampled near the end
of the bus cycle to confirm the physical data bus size
applicable to the current cycle. Negation of BS16
Y
indicates a 32-bit size, and assertion indicates a
16-bit bus size.
If 16-bit bus size is indicated, the Intel386 DX auto-
matically responds as required to complete the
transfer on a 16-bit data bus. Depending on the size
and alignment of the operand, another 16-bit bus
cycle may be required. Table 5-7 provides all details.
When necessary, the Intel386 DX performs an addi-
tional 16-bit bus cycle, using D0–D15 in place of
D16–D31.
Terminating a read cycle or write cycle, like any bus
cycle, requires acknowledging the cycle by asserting
the READY
Y
input. Until acknowledged, the proces-
sor inserts wait states into the bus cycle, to allow
adjustment for the speed of any external device. Ex-
ternal hardware, which has decoded the address
and bus cycle type asserts the READY
Y
input at the
appropriate time.
231630–15
Idle states are shown here for diagram variety only. Write cycles are
not
always followed by an idle state. An active bus cycle can immediately
follow the write cycle.
Figure 5-11. Various Bus Cycles and Idle States with Non-Pipelined Address (zero wait states)
76
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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