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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 12/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
cal space of the machine, 4 Gbytes (2
32
bytes). If a
maximum
sized
segment
FFFFFFFFH) it should be Dword aligned (i.e., the
least two significant bits of the segment base should
be zero). This will avoid a segment limit violation (ex-
ception 13) caused by the wrap around. In Real Ad-
dress Mode, the maximum segment size is fixed at
64 Kbytes (2
16
bytes).
is
used
(limit
e
The six segments addressable at any given moment
are defined by the segment registers CS, SS, DS,
ES, FS and GS. The selector in CS indicates the
current code segment; the selector in SS indicates
the current stack segment; the selectors in DS, ES,
FS and GS indicate the current data segments.
2.3.5 Segment Descriptor Registers
The segment descriptor registers are not program-
mer visible, yet it is very useful to understand their
content. Inside the Intel386 DX, a descriptor register
(programmer invisible) is associated with each pro-
grammer-visible segment register, as shown by Fig-
ure 2-4. Each descriptor register holds a 32-bit seg-
ment base address, a 32-bit segment limit, and the
other necessary segment attributes.
When a selector value is loaded into a segment reg-
ister, the associated descriptor register is automati-
cally updated with the correct information. In Real
Address Mode, only the base address is updated
directly (by shifting the selector value four bits to the
left), since the segment maximum limit and attributes
are fixed in Real Mode. In Protected Mode, the base
address, the limit, and the attributes are all updated
per the contents of the segment descriptor indexed
by the selector.
Whenever a memory reference occurs, the segment
descriptor register associated with the segment be-
ing used is automatically involved with the memory
reference. The 32-bit segment base address be-
comes a component of the linear address calcula-
tion, the 32-bit limit is used for the limit-check opera-
tion, and the attributes are checked against the type
of memory reference requested.
2.3.6 Control Registers
The Intel386 DX has three control registers of 32
bits, CR0, CR2 and CR3, to hold machine state of a
global nature (not specific to an individual task).
These registers, along with System Address Regis-
ters described in the next section, hold machine
state that affects all tasks in the system. To access
the Control Registers, load and store instructions
are defined.
CR0: Machine Control Register (includes 80286
Machine Status Word)
CR0, shown in Figure 2-5, contains 6 defined bits for
control and status purposes. The low-order 16 bits
of CR0 are also known as the Machine Status Word,
MSW, for compatibility with 80286 Protected Mode.
LMSW and SMSW instructions are taken as special
aliases of the load and store CR0 operations, where
only the low-order 16 bits of CR0 are involved. For
compatibility with 80286 operating systems the In-
tel386 DX LMSW instructions work in an identical
fashion to the LMSW instruction on the 80286. (i.e. It
only operates on the low-order 16-bits of CR0 and it
ignores the new bits in CR0.) New Intel386 DX oper-
ating systems should use the MOV CR0, Reg in-
struction.
The defined CR0 bits are described below.
PG
(Paging Enable, bit 31)
the PG bit is set to enable the on-chip paging
unit. It is reset to disable the on-chip paging
unit.
R
(reserved, bit 4)
This bit is reserved by Intel. When loading CR0
care should be taken to not alter the value of
this bit.
31
24 23
16 15
8 7
0
P
G
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R
T E M PCR0
X
Y
MSW
NOTE:
0
indicates Intel reserved: Do not define; SEE SECTION 2.3.10
Figure 2-5. Control Register 0
12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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