參數(shù)資料
型號: intel386 DX
廠商: Intel Corp.
英文描述: 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述: 32位CHMOS微處理器集成內(nèi)存管理(32位CHMOS微處理器帶集成存儲管理)
文件頁數(shù): 37/139頁
文件大?。?/td> 1587K
代理商: INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
GDT. Generally the GDT contains code and data
segments used by the operating systems and task
state segments, and descriptors for the LDTs in a
system.
The first slot of the Global Descriptor Table corre-
sponds to the null selector and is not used. The null
selector defines a null pointer value.
4.3.3.3 LOCAL DESCRIPTOR TABLE
LDTs contain descriptors which are associated with
a given task. Generally, operating systems are de-
signed so that each task has a separate LDT. The
LDT may contain only code, data, stack, task gate,
and call gate descriptors. LDTs provide a mecha-
nism for isolating a given task’s code and data seg-
ments from the rest of the operating system, while
the GDT contains descriptors for segments which
are common to all tasks. A segment cannot be ac-
cessed by a task if its segment descriptor does not
exist in either the current LDT or the GDT. This pro-
vides both isolation and protection for a task’s seg-
ments, while still allowing global data to be shared
among tasks.
Unlike the 6 byte GDT or IDT registers which contain
a base address and limit, the visible portion of the
LDT register contains only a 16-bit selector. This se-
lector refers to a Local Descriptor Table descriptor in
the GDT.
4.3.3.4 INTERRUPT DESCRIPTOR TABLE
The third table needed for Intel386 DX systems is
the Interrupt Descriptor Table. (See Figure 4-4.) The
IDT contains the descriptors which point to the loca-
tion of up to 256 interrupt service routines. The IDT
may contain only task gates, interrupt gates, and
trap gates. The IDT should be at least 256 bytes in
size in order to hold the descriptors for the 32 Intel
Reserved Interrupts. Every interrupt used by a sys-
tem must have an entry in the IDT. The IDT entries
are referenced via INT instructions, external inter-
rupt vectors, and exceptions. (See 2.9
Interrupts).
231630–58
Figure 4-4. Interrupt Descriptor
Table Register Use
4.3.4 Descriptors
4.3.4.1 DESCRIPTOR ATTRIBUTE BITS
The object to which the segment selector points to
is called a descriptor. Descriptors are eight byte
quantities which contain attributes about a given re-
gion of linear address space (i.e. a segment). These
attributes include the 32-bit base linear address of
the segment, the 20-bit length and granularity of the
segment, the protection level, read, write or execute
privileges, the default size of the operands (16-bit or
31
0
BYTE
ADDRESS
SEGMENT BASE 15 . . . 0
SEGMENT LIMIT 15 . . . 0
0
BASE 31 . . . 24
G
D
0
AVL
LIMIT
19 . . . 16
P
DPL
S
TYPE
A
BASE
23 . . . 16
a
4
BASE
LIMIT
P
DPL
S
TYPE
A
G
D
0
AVL
Base Address of the segment
The length of the segment
Present Bit
1
e
Present
Descriptor Privilege Level 0–3
Segment Descriptor
Type of Segment
Accessed Bit
Granularity Bit
Default Operation Size (recognized in code segment descriptors only)
Bit must be zero (0) for compatibility with future processors
Available field for user or OS
0
e
Not Present
0
e
System Descriptor
1
e
Code or Data Segment Descriptor
1
e
Segment length is page granular
0
e
Segment length is byte granular
1
e
32-bit segment
0
e
16-bit segment
NOTE:
In a maximum-size segment (ie. a segment with G
e
1 and segment limit 19...0
e
FFFFFH), the lowest 12 bits of the
segment base should be zero (ie. segment base 11...000
e
000H).
Figure 4-5. Segment Descriptors
37
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