- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄377496 > intel386 DX (Intel Corp.) 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理) PDF資料下載
參數(shù)資料
| 型號(hào)： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理） |
| 文件頁(yè)數(shù)： | 8/139頁(yè) |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)
Intel386
TM
DX MICROPROCESSOR
2. BASE ARCHITECTURE
2.1 INTRODUCTION
The Intel386 DX consists of a central processing
unit, a memory management unit and a bus inter-
face.
The central processing unit consists of the execu-
tion unit and instruction unit. The execution unit con-
tains the eight 32-bit general purpose registers
which are used for both address calculation, data
operations and a 64-bit barrel shifter used to speed
shift, rotate, multiply, and divide operations. The
multiply and divide logic uses a 1-bit per cycle algo-
rithm. The multiply algorithm stops the iteration
when the most significant bits of the multiplier are all
zero. This allows typical 32-bit multiplies to be exe-
cuted in under one microsecond. The instruction unit
decodes the instruction opcodes and stores them in
the decoded instruction queue for immediate use by
the execution unit.
The memory management unit (MMU) consists of a
segmentation unit and a paging unit. Segmentation
allows the managing of the logical address space by
providing an extra addressing component, one that
allows easy code and data relocatability, and effi-
cient sharing. The paging mechanism operates be-
neath and is transparent to the segmentation pro-
cess, to allow management of the physical address
space. Each segment is divided into one or more 4K
byte pages. To implement a virtual memory system,
the Intel386 DX supports full restartability for all
page and segment faults.
Memory is organized into one or more variable
length segments, each up to four gigabytes in size. A
given region of the linear address space, a segment,
can have attributes associated with it. These attri-
butes include its location, size, type (i.e. stack, code
or data), and protection characteristics. Each task
on an Intel386 DX can have a maximum of 16,381
segments of up to four gigabytes each, thus provid-
ing 64 terabytes (trillion bytes) of virtual memory to
each task.
The segmentation unit provides four-levels of pro-
tection for isolating and protecting applications and
the operating system from each other. The hardware
enforced protection allows the design of systems
with a high degree of integrity.
The Intel386 DX has two modes of operation: Real
Address Mode (Real Mode), and Protected Virtual
Address Mode (Protected Mode). In Real Mode the
Intel386 DX operates as a very fast 8086, but with
32-bit extensions if desired. Real Mode is required
primarily to setup the processor for Protected Mode
operation. Protected Mode provides access to the
sophisticated memory management, paging and
privilege capabilities of the processor.
Within Protected Mode, software can perform a task
switch to enter into tasks designated as Virtual 8086
Mode tasks. Each such task behaves with 8086 se-
mantics, thus allowing 8086 software (an application
program, or an entire operating system) to execute.
The Virtual 8086 tasks can be isolated and protect-
ed from one another and the host Intel386 DX oper-
ating system, by the use of paging, and the I/O Per-
mission Bitmap.
Finally, to facilitate high performance system hard-
ware designs, the Intel386 DX bus interface offers
address pipelining, dynamic data bus sizing, and di-
rect Byte Enable signals for each byte of the data
bus. These hardware features are described fully be-
ginning in Section 5.
2.2 REGISTER OVERVIEW
The Intel386 DX has 32 register resources in the
following categories:
#
General Purpose Registers
#
Segment Registers
#
Instruction Pointer and Flags
#
Control Registers
#
System Address Registers
#
Debug Registers
#
Test Registers.
The registers are a superset of the 8086, 80186 and
80286 registers, so all 16-bit 8086, 80186 and
80286 registers are contained within the 32-bit In-
tel386 DX.
Figure 2-1 shows all of Intel386 DX base architec-
ture registers, which include the general address
and data registers, the instruction pointer, and the
flags register. The contents of these registers are
task-specific, so these registers are automatically
loaded with a new context upon a task switch opera-
tion.
The base architecture also includes six directly ac-
cessible segments, each up to 4 Gbytes in size. The
segments are indicated by the selector values
placed in Intel386 DX segment registers of Figure
2-1. Various selector values can be loaded as a pro-
gram executes, if desired.
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。