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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 56/139頁 |
| 文件大小： | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
U/S
W/R
Access Type
0
0
1
1
0
1
0
1
Supervisor
*
Read
Supervisor Write
User Read
User Write
*
Descriptor table access will fault with U/S
e
0, even if the program
is executing at level 3.
Figure 4-23B. Type of Access
Causing Page Fault
4.5.6 Operating System
Responsibilities
The Intel386 DX takes care of the page address
translation process, relieving the burden from an op-
erating system in a demand-paged system. The op-
erating system is responsible for setting up the initial
page tables, and handling any page faults. The oper-
ating system also is required to invalidate (i.e. flush)
the TLB when any changes are made to any of the
page table entries. The operating system must re-
load CR3 to cause the TLB to be flushed.
Setting up the tables is simply a matter of loading
CR3 with the address of the Page Directory, and
allocating space for the Page Directory and the
Page Tables. The primary responsibility of the oper-
ating system is to implement a swapping policy and
handle all of the page faults.
A final concern of the operating system is to ensure
that the TLB cache matches the information in the
paging tables. In particular, any time the operating
system sets the P present bit of page table entry to
zero, the TLB must be flushed. Operating systems
may want to take advantage of the fact that CR3 is
stored as part of a TSS, to give every task or group
of tasks its own set of page tables.
4.6 VIRTUAL 8086 ENVIRONMENT
4.6.1 Executing 8086 Programs
The Intel386 DX allows the execution of 8086 appli-
cation programs in both Real Mode and in the Virtual
8086 Mode (Virtual Mode). Of the two methods, Vir-
tual 8086 Mode offers the system designer the most
flexibility. The Virtual 8086 Mode allows the execu-
tion of 8086 applications, while still allowing the sys-
tem designer to take full advantage of the Intel386
DX protection mechanism. In particular, the Intel386
DX allows the simultaneous execution of 8086 oper-
ating systems and its applications, and an Intel386
DX operating system and both 80286 and Intel386
DX applications. Thus, in a multi-user Intel386 DX
computer, one person could be running an MS-DOS
spreadsheet, another person using MS-DOS, and a
third person could be running multiple Unix utilities
and applications. Each person in this scenario would
believe that he had the computer completely to him-
self. Figure 4-24 illustrates this concept.
4.6.2 Virtual 8086 Mode Addressing
Mechanism
One of the major differences between Intel386 DX
Real and Protected modes is how the segment se-
lectors are interpreted. When the processor is exe-
cuting in Virtual 8086 Mode the segment registers
are used in an identical fashion to Real Mode. The
contents of the segment register is shifted left 4 bits
and added to the offset to form the segment base
linear address.
The Intel386 DX allows the operating system to
specify which programs use the 8086 style address
mechanism, and which programs use Protected
Mode addressing, on a per task basis. Through the
use of paging, the one megabyte address space of
the Virtual Mode task can be mapped to anywhere in
the 4 gigabyte linear address space of the Intel386
DX. Like Real Mode, Virtual Mode effective address-
es (i.e., segment offsets) that exceed 64K byte will
cause an exception 13. However, these restrictions
should not prove to be important, because most
tasks running in Virtual 8086 Mode will simply be
existing 8086 application programs.
4.6.3 Paging In Virtual Mode
The paging hardware allows the concurrent running
of multiple Virtual Mode tasks, and provides protec-
tion and operating system isolation. Although it is
not strictly necessary to have the paging hardware
enabled to run Virtual Mode tasks, it is needed in
order to run multiple Virtual Mode tasks or to relo-
cate the address space of a Virtual Mode task to
physical address space greater than one megabyte.
The paging hardware allows the 20-bit linear ad-
dress produced by a Virtual Mode program to be
divided into up to 256 pages. Each one of the pages
can be located anywhere within the maximum 4 giga-
byte physical address space of the Intel386 DX. In
addition, since CR3 (the Page Directory Base Regis-
ter) is loaded by a task switch, each Virtual Mode
task can use a different mapping scheme to map
pages to different physical locations. Finally, the
paging hardware allows the sharing of the 8086 op-
56
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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