參數(shù)資料
型號(hào)： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理）
文件頁(yè)數(shù)： 48/139頁(yè)
文件大?。?/td> 1587K
代理商： INTEL386 DX
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Intel386
TM
DX MICROPROCESSOR
Table 4-3. Descriptor Types Used for Control Transfer
Control Transfer Types
Operation Types
Descriptor
Referenced
Descriptor
Table
Intersegment within the same privilege level
JMP, CALL, RET, IRET
*
Code Segment
GDT/LDT
Intersegment to the same or higher privilege level
Interrupt within task may change CPL
CALL
Call Gate
GDT/LDT
Interrupt Instruction,
Exception, External
Interrupt
Trap or
Interrupt
Gate
IDT
Intersegment to a lower privilege level
(changes task CPL)
RET, IRET
*
Code Segment
GDT/LDT
CALL, JMP
Task State
Segment
GDT
Task Switch
CALL, JMP
Task Gate
GDT/LDT
IRET
**
Interrupt Instruction,
Exception, External
Interrupt
Task Gate
IDT
*
NT (Nested Task bit of flag register)
e
0
**
NT (Nested Task bit of flag register)
e
1
or a jump to another routine. There are five types of
control transfers which are summarized in Table 4-3.
Many of these transfers result in a privilege level
transfer. Changing privilege levels is done only via
control transfers, by using gates, task switches, and
interrupt or trap gates.
Control transfers can only occur if the operation
which loaded the selector references the correct de-
scriptor type. Any violation of these descriptor usage
rules will cause an exception 13 (e.g. JMP through a
call gate, or IRET from a normal subroutine call).
In order to provide further system security, all control
transfers are also subject to the privilege rules.
The privilege rules require that:
D Privilege level transitions can only occur via
gates.
D JMPs can be made to a non-conforming code
segment with the same privilege or to a conform-
ing code segment with greater or equal privilege.
D CALLs can be made to a non-conforming code
segment with the same privilege or via a gate to a
more privileged level.
D Interrupts handled within the task obey the same
privilege rules as CALLs.
D Conforming Code segments are accessible by
privilege levels which are the same or less privi-
leged than the conforming-code segment’s DPL.
D Both the requested privilege level (RPL) in the
selector pointing to the gate and the task’s CPL
must be of equal or greater privilege than the
gate’s DPL.
D The code segment selected in the gate must be
the same or more privileged than the task’s CPL.
D Return instructions that do not switch tasks can
only return control to a code segment with same
or less privilege.
D Task switches can be performed by a CALL,
JMP, or INT which references either a task gate
or task state segment who’s DPL is less privi-
leged or the same privilege as the old task’s CPL.
Any control transfer that changes CPL within a task
causes a change of stacks as a result of the privi-
lege level change. The initial values of SS:ESP for
privilege levels 0, 1, and 2 are retained in the task
state segment (see section 4.4.6
Task Switching
).
During a JMP or CALL control transfer, the new
stack pointer is loaded into the SS and ESP regis-
ters and the previous stack pointer is pushed onto
the new stack.
When RETurning to the original privilege level, use
of the lower-privileged stack is restored as part of
the RET or IRET instruction operation. For subrou-
tine calls that pass parameters on the stack and
cross privilege levels, a fixed number of words (as
specified in the gate’s word count field) are copied
from the previous stack to the current stack. The
inter-segment RET instruction with a stack adjust-
ment value will correctly restore the previous stack
pointer upon return.
48
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PDF描述
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INTEL387SX 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR
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