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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 91/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
231630–30
NOTE:
HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold (t
23
and t
24
) require-
ments are met. This waveform is useful for determining Hold Acknowledge latency.
Figure 5-26. Requesting Hold from Active Bus (NA
Y
negated)
cause the self-test to report a failure when no true
failure exists. The additional RESET pulse width is
required to clear additional state prior to a valid self-
test.
Provided the RESET falling edge meets setup and
hold times t
25
and t
26
, the internal processor clock
phase is defined at that time, as illustrated by Figure
5-28 and Figure 7-7.
A Intel386 DX self-test may be requested at the time
RESET is negated by having the BUSY
Y
input at a
LOW level, as shown in Figure 5-28. The self-test
requires (2
20
)
a
approximately 60 CLK2 periods to
complete. The self-test duration is not affected by
the test results. Even if the self-test indicates a prob-
lem, the Intel386 DX attempts to proceed with the
reset sequence afterwards.
After the RESET falling edge (and after the self-test
if it was requested) the Intel386 DX performs an in-
ternal initialization sequence for approximately 350
to 450 CLK2 periods.
The Intel386 DX samples its ERROR
Y
input some
time after the falling edge of RESET and before exe-
cuting the first ESC instruction. During this sampling
period BUSY
Y
must be HIGH. If ERROR
Y
was
sampled active, the Intel386 DX employs the 32-bit
protocol of the Intel387 DX. Even though this proto-
col was selected, it is still necessary to use a soft-
ware recognition test to determine the presence or
identity of the coprocessor and to assure compatibil-
ity with future processors. (See Chapter 11 of the
Intel386 DX Programmer’s Reference Manual, Order
Y
230985-002).
91
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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