參數(shù)資料
型號: intel386 DX
廠商: Intel Corp.
英文描述: 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述: 32位CHMOS微處理器集成內存管理(32位CHMOS微處理器帶集成存儲管理)
文件頁數(shù): 38/139頁
文件大?。?/td> 1587K
代理商: INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
32-bit), and the type of segment. All of the attribute
information about a segment is contained in 12 bits
in the segment descriptor. Figure 4-5 shows the gen-
eral format of a descriptor. All segments on the In-
tel386 DX have three attribute fields in common: the
P
bit, the
DPL
bit, and the
S
bit. The Present
P
bit is
1 if the segment is loaded in physical memory, if
P
e
0 then any attempt to access this segment caus-
es a not present exception (exception 11). The De-
scriptor Privilege Level
DPL
is a two-bit field which
specifies the protection level 0–3 associated with a
segment.
The Intel386 DX has two main categories of seg-
ments system segments and non-system segments
(for code and data). The segment
S
bit in the seg-
ment descriptor determines if a given segment is a
system segment or a code or data segment. If the S
bit is 1 then the segment is either a code or data
segment, if it is 0 then the segment is a system seg-
ment.
4.3.4.2 Intel386
TM
DX CODE, DATA
DESCRIPTORS (S
e
1)
Figure 4-6 shows the general format of a code and
data descriptor and Table 4-1 illustrates how the bits
in the Access Rights Byte are interpreted.
31
0
SEGMENT BASE 15 . . . 0
SEGMENT LIMIT 15 . . . 0
0
LIMIT
19 . . . 16
ACCESS
RIGHTS
BYTE
BASE
BASE 31 . . . 24
G
D/B
0
AVL
23 . . . 16
a
4
D/B
1
e
Default Instructions Attributes are 32-Bits
0
e
Default Instruction Attributes are 16-Bits
Available field for user or OS
AVL
G
Granularity Bit
1
e
Segment length is page granular
0
e
Segment length is byte granular
Bit must be zero (0) for compatibility with future processors
0
NOTE:
In a maximum-size segment (ie. a segment with G
e
1 and segment limit 19...0
e
FFFFFH), the lowest 12 bits of the
segment base should be zero (ie. segment base 11...000
e
000H).
Figure 4-6. Segment Descriptors
Table 4-1. Access Rights Byte Definition for Code and Data Descriptions
Bit
Name
Function
Position
7
Present (P)
P
e
1
P
e
0
Segment is mapped into physical memory.
No mapping to physical memory exits, base and limit are not
used.
Segment privilege attribute used in privilege tests.
6–5
Descriptor Privilege
Level (DPL)
Segment Descrip-
tor (S)
4
S
e
1
S
e
0
Code or Data (includes stacks) segment descriptor
System Segment Descriptor or Gate Descriptor
3
2
Executable (E)
Expansion Direc-
tion (ED)
Writeable (W)
E
e
0
ED 0
ED
e
1 Expand down segment, offsets must be
l
limit.
W
e
0
Data segment may not be written into.
W
e
1
Data segment may be written into.
Descriptor type is data segment:
Expand up segment, offsets must be
s
limit.
If
Data
Segment
(S
e
1,
E
e
0)
1
Type
Field
Definition
*
3
2
Executable (E)
Conforming (C)
E
e
1
C
e
1
Descriptor type is code segment:
Code segment may only be executed when
CPL
t
DPL and CPL remains unchanged.
Code segment may not be read.
Code segment may be read.
If
Code
Segment
(S
e
1,
E
e
1)
1
Readable (R)
R
e
0
R
e
1
*
0
Accessed (A)
A
e
0
A
e
1
Segment has not been accessed.
Segment selector has been loaded into segment register or
used by selector test instructions.
38
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