參數(shù)資料
型號(hào)： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理）
文件頁數(shù)： 101/139頁
文件大?。?/td> 1587K
代理商： INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
Table 6-1. Intel386
TM
DX Instruction Set Clock Count Summary
(Continued)
CLOCK COUNT
NOTES
Real
Address
Mode or
Virtual
8086
Mode
Real
Address Protected
Mode or
Virtual
8086
Mode
INSTRUCTION
FORMAT
Protected
Virtual
Address
Mode
Virtual
Address
Mode
REPEATED STRING MANIPULATION
(Continued)
REPNE CMPS
e
Compare String
(Find Match)
1 1 1 1 0 0 1 0
1 0 1 0 0 1 1 w
8086 Mode
Clk Count
Virtual
5
a
9n
5
a
9n
b
h
REP INS
e
Input String
1 1 1 1 0 0 1 0
0 1 1 0 1 1 0 w
2
28
a
6n
14
a
6n
8
a
6n
*
/28
a
6n
**
b
h, m
REP LODS
e
Load String
1 1 1 1 0 0 1 0
1 0 1 0 1 1 0 w
5
a
6n
5
a
6n
b
h
REP MOVS
e
Move String
1 1 1 1 0 0 1 0
1 0 1 0 0 1 0 w
8
a
4n
8
a
4n
b
h
REP OUTS
e
Output String
1 1 1 1 0 0 1 0
0 1 1 0 1 1 1 w
2
26
a
5n
12
a
5n
6
a
5n
*
/26
a
5n
**
b
h, m
REPE SCAS
e
Scan String
(Find Non-AL/AX/EAX)
1 1 1 1 0 0 1 1
1 0 1 0 1 1 1 w
5
a
8n
5
a
8n
b
h
REPNE SCAS
e
Scan String
(Find AL/AX/EAX)
1 1 1 1 0 0 1 0
1 0 1 0 1 1 1 w
5
a
8n
5
a
8n
b
h
REP STOS
e
Store String
1 1 1 1 0 0 1 0
1 0 1 0 1 0 1 w
5
a
5n
5
a
5n
b
h
BIT MANIPULATION
BSF
e
Scan Bit Forward
0 0 0 0 1 1 1 1
1 0 1 1 1 1 0 0 mod reg
r/m
11
a
3n
11
a
3n
b
h
BSR
e
Scan Bit Reverse
0 0 0 0 1 1 1 1
1 0 1 1 1 1 0 1 mod reg
r/m
9
a
3n
9
a
3n
b
h
BT
e
Test Bit
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 0 0
r/m immed 8-bit data
3/6
3/6
b
h
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 0 0 0 1 1 mod reg
r/m
3/12
3/12
b
h
BTC
e
Test Bit and Complement
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 1 1
r/m immed 8-bit data
6/8
6/8
b
h
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 1 mod reg
r/m
6/13
6/13
b
h
BTR
e
Test Bit and Reset
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 1 0
r/m immed 8-bit data
6/8
6/8
b
h
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 1 0 0 1 1 mod reg
r/m
6/13
6/13
b
h
BTS
e
Test Bit and Set
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0 mod 1 0 1
r/m immed 8-bit data
6/8
6/8
b
h
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 0 1 0 1 1 mod reg
r/m
6/13
6/13
b
h
CONTROL TRANSFER
CALL
e
Call
Direct Within Segment
1 1 1 0 1 0 0 0
full displacement
7
a
m
7
a
m
b
r
Register/Memory
Indirect Within Segment
1 1 1 1 1 1 1 1 mod 0 1 0
r/m
10
a
m
7
a
m/
10
a
m
7
a
m/
b
h, r
Direct Intersegment
1 0 0 1 1 0 1 0 unsigned full offset, selector
17
a
m
34
a
m
b
j,k,r
NOTES:
2
Clock count shown applies if I/O permission allows I/O to the port in virtual 8086 mode. If I/O bit map denies permission
exception 13 fault occurs; refer to clock counts for INT 3 instruction.
*
If CPL
s
IOPL
**
If CPL
l
IOPL
101
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