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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 51/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
231630–65
Figure 4-16. 80286 TSS
When a CALL or INT instruction initiates a task
switch, the new TSS will be marked busy and the
back link field of the new TSS set to the old TSS
selector. The NT bit of the new task is set by CALL
or INT initiated task switches. An interrupt that does
not cause a task switch will clear NT. (The NT bit will
be restored after execution of the interrupt handler)
NT may also be set or cleared by POPF or IRET
instructions.
The Intel386 DX task state segment is marked busy
by changing the descriptor type field from TYPE 9H
to TYPE BH. An 80286 TSS is marked busy by
changing the descriptor type field from TYPE 1 to
TYPE 3. Use of a selector that references a busy
task state segment causes an exception 13.
The Virtual Mode (VM) bit 17 is used to indicate if a
task, is a virtual 8086 task. If VM
e
1, then the tasks
will use the Real Mode addressing mechanism. The
virtual 8086 environment is only entered and exited
via a task switch (see section 4.6
Virtual Mode
).
The coprocessor’s state is not automatically saved
when a task switch occurs, because the incoming
task may not use the coprocessor. The Task
Switched (TS) Bit (bit 3 in the CR0) helps deal with
the coprocessor’s state in a multi-tasking environ-
ment. Whenever the Intel386 DX switches tasks, it
sets the TS bit. The Intel386 DX detects the first use
of a processor extension instruction after a task
switch and causes the processor extension not
available exception 7. The exception handler for ex-
ception 7 may then decide whether to save the state
of the coprocessor. A processor extension not pres-
ent exception (7) will occur when attempting to exe-
cute an ESC or WAIT instruction if the Task
Switched and Monitor coprocessor extension bits
are both set (i.e. TS
e
1 and MP
e
1).
The
T
bit in the Intel386 DX TSS indicates that the
processor should generate a debug exception when
switching to a task. If T
e
1 then upon entry to a
new task a debug exception 1 will be generated.
4.4.7 Initialization and Transition to
Protected Mode
Since the Intel386 DX begins executing in Real
Mode immediately after RESET it is necessary to
initialize the system tables and registers with the ap-
propriate values.
The GDT and IDT registers must refer to a valid GDT
and IDT. The IDT should be at least 256 bytes long,
and GDT must contain descriptors for the initial
code, and data segments. Figure 4-17 shows the
tables and Figure 4-18 the descriptors needed for a
simple Protected Mode Intel386 DX system. It has a
single code and single data/stack segment each
four gigabytes long and a single privilege level PL
e
0.
The actual method of enabling Protected Mode is to
load CR0 with the PE bit set, via the MOV CR0, R/M
instruction. This puts the Intel386 DX in Protected
Mode.
After enabling Protected Mode, the next instruction
should execute an intersegment JMP to load the CS
register and flush the instruction decode queue. The
final step is to load all of the data segment registers
with the initial selector values.
An alternate approach to entering Protected Mode
which is especially appropriate for multi-tasking op-
erating systems, is to use the built in task-switch to
load all of the registers. In this case the GDT would
contain two TSS descriptors in addition to the code
and data descriptors needed for the first task. The
first JMP instruction in Protected Mode would jump
to the TSS causing a task switch and loading all of
the registers with the values stored in the TSS. The
Task State Segment Register should be initialized to
point to a valid TSS descriptor since a task switch
saves the state of the current task in a task state
segment.
51
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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