參數(shù)資料
型號： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理）
文件頁數(shù)： 59/139頁
文件大?。?/td> 1587K
代理商： INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
4.6.6 Entering and Leaving Virtual
8086 Mode
Virtual 8086 mode is entered by executing an IRET
instruction (at CPL
e
0), or Task Switch (at any CPL)
to an Intel386 DX task whose Intel386 DX TSS has a
FLAGS image containing a 1 in the VM bit position
while the processor is executing in Protected Mode.
That is, one way to enter Virtual 8086 mode is to
switch to a task with an Intel386 DX TSS that has a
1 in the VM bit in the EFLAGS image. The other way
is to execute a 32-bit IRET instruction at privilege
level 0, where the stack has a 1 in the VM bit in the
EFLAGS image. POPF does not affect the VM bit,
even if the processor is in Protected Mode or level 0,
and so cannot be used to enter Virtual 8086 Mode.
PUSHF always pushes a 0 in the VM bit, even if the
processor is in Virtual 8086 Mode, so that a program
cannot tell if it is executing in REAL mode, or in Vir-
tual 8086 mode.
The VM bit can be set by executing an IRET instruc-
tion only at privilege level 0, or by any instruction or
Interrupt which causes a task switch in Protected
Mode (with VM
e
1 in the new FLAGS image), and
can be cleared only by an interrupt or exception in
Virtual 8086 Mode. IRET and POPF instructions exe-
cuted in REAL mode or Virtual 8086 mode will not
change the value in the VM bit.
The transition out of virtual 8086 mode to Intel386
DX protected mode occurs only on receipt of an in-
terrupt or exception (such as due to a sensitive in-
struction). In Virtual 8086 mode, all interrupts and
exceptions vector through the protected mode IDT,
and enter an interrupt handler in protected Intel386
DX mode. That is, as part of interrupt processing,
the VM bit is cleared.
Because the matching IRET must occur from level 0,
if an Interrupt or Trap Gate is used to field an inter-
rupt or exception out of Virtual 8086 mode, the Gate
must perform an inter-level interrupt only to level 0.
Interrupt or Trap Gates through conforming seg-
ments, or through segments with DPL
l
0, will raise a
GP fault with the CS selector as the error code.
4.6.6.1 TASK SWITCHES TO/FROM VIRTUAL
8086 MODE
Tasks which can execute in virtual 8086 mode must
be described by a TSS with the new Intel386 DX
format (TYPE 9 or 11 descriptor).
A task switch out of virtual 8086 mode will operate
exactly the same as any other task switch out of a
task with an Intel386 DX TSS. All of the programmer
visible state, including the FLAGS register with the
VM bit set to 1, is stored in the TSS. The segment
registers in the TSS will contain 8086 segment base
values rather than selectors.
A task switch into a task described by an Intel386
DX TSS will have an additional check to determine if
the incoming task should be resumed in virtual 8086
mode. Tasks described by 80286 format TSSs can-
not be resumed in virtual 8086 mode, so no check is
required there (the FLAGS image in 80286 format
TSS has only the low order 16 FLAGS bits). Before
loading the segment register images from an In-
tel386 DX TSS, the FLAGS image is loaded, so that
the segment registers are loaded from the TSS im-
age as 8086 segment base values. The task is now
ready to resume in virtual 8086 execution mode.
4.6.6.2 TRANSITIONS THROUGH TRAP AND
INTERRUPT GATES, AND IRET
A task switch is one way to enter or exit virtual 8086
mode. The other method is to exit through a Trap or
Interrupt gate, as part of handling an interrupt, and
to enter as part of executing an IRET instruction.
The transition out must use an Intel386 DX Trap
Gate (Type 14), or Intel386 DX Interrupt Gate (Type
15), which must point to a non-conforming level 0
segment (DPL
e
0) in order to permit the trap han-
dler to IRET back to the Virtual 8086 program. The
Gate must point to a non-conforming level 0 seg-
ment to perform a level switch to level 0 so that the
matching IRET can change the VM bit. Intel386 DX
gates must be used, since 80286 gates save only
the low 16 bits of the FLAGS register, so that the VM
bit will not be saved on transitions through the
80286 gates. Also, the 16-bit IRET (presumably)
used to terminate the 80286 interrupt handler will
pop only the lower 16 bits from FLAGS, and will not
affect the VM bit. The action taken for an Intel386
DX Trap or Interrupt gate if an interrupt occurs while
the task is executing in virtual 8086 mode is given by
the following sequence.
(1) Save the FLAGS register in a temp to push later.
Turn off the VM and TF bits, and if the interrupt is
serviced by an Interrupt Gate, turn off IF also.
(2) Interrupt and Trap gates must perform a level
switch from 3 (where the VM86 program exe-
cutes) to level 0 (so IRET can return). This pro-
cess involves a stack switch to the stack given in
the TSS for privilege level 0. Save the Virtual
8086 Mode SS and ESP registers to push in a
later step. The segment register load of SS will
be done as a Protected Mode segment load,
since the VM bit was turned off above.
(3) Push the 8086 segment register values onto the
new stack, in the order: GS, FS, DS, ES. These
are pushed as 32-bit quantities, with undefined
values in the upper 16 bits. Then load these 4
registers with null selectors (0).
59
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