參數(shù)資料
型號(hào)： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理）
文件頁數(shù)： 27/139頁
文件大?。?/td> 1587K
代理商： INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
2.9.7 Instruction Restart
The Intel386 DX fully supports restarting all instruc-
tions after faults. If an exception is detected in the
instruction to be executed (exception categories 4
through 10 in Table 2-6b), the Intel386 DX invokes
the appropriate exception service routine. The In-
tel386 DX is in a state that permits restart of the
instruction, for all cases but those in Table 2-6c.
Note that all such cases are easily avoided by prop-
er design of the operating system.
Table 2-6c. Conditions Preventing
Instruction Restart
A. An instruction causes a task switch to a task
whose Task State Segment is
partially
‘‘not
present’’. (An entirely ‘‘not present’’ TSS is re-
startable.) Partially present TSS’s can be
avoided either by keeping the TSS’s of such
tasks present in memory, or by aligning TSS
segments to reside entirely within a single 4K
page (for TSS segments of 4K bytes or less).
B. A coprocessor operand wraps around the top
of a 64K-byte segment or a 4G-byte segment,
and spans three pages, and the page holding
the middle portion of the operand is ‘‘not pres-
ent.’’ This condition can be avoided by starting
at a page boundary
any segments containing
coprocessor operands if the segments are ap-
proximately 64K-200 bytes or larger (i.e. large
enough for wraparound of the coprocessor
operand to possibly occur).
Note that these conditions are avoided by using
the operating system designs mentioned in this
table.
2.9.8 Double Fault
A Double Fault (exception 8) results when the proc-
essor attempts to invoke an exception service rou-
tine for the segment exceptions (10, 11, 12 or 13),
but in the process of doing so, detects an exception
other than
a Page Fault (exception 14).
A Double Fault (exception 8) will also be generated
when the processor attempts to invoke the Page
Fault (exception 14) service routine, and detects an
exception other than a second Page Fault. In any
functional system, the entire Page Fault service rou-
tine must remain ‘‘present’’ in memory.
Double page faults however do not raise the double
fault exception. If a second page fault occurs while
the processor is attempting to enter the service rou-
tine for the first time, then the processor will invoke
the page fault (exception 14) handler a second time,
rather than the double fault (exception 8) handler. A
subsequent fault, though, will lead to shutdown.
When a Double Fault occurs, the Intel386 DX in-
vokes the exception service routine for exception 8.
2.10 RESET AND INITIALIZATION
When the processor is initialized or Reset the regis-
ters have the values shown in Table 2-7. The In-
tel386 DX will then start executing instructions near
the top of physical memory, at location FFFFFFF0H.
When the first InterSegment Jump or Call is execut-
ed, address lines A20-31 will drop low for CS-rela-
tive memory cycles, and the Intel386 DX will only
execute instructions in the lower one megabyte of
physical memory. This allows the system designer to
use a ROM at the top of physical memory to initialize
the system and take care of Resets.
RESET forces the Intel386 DX to terminate all exe-
cution and local bus activity. No instruction execu-
tion or bus activity will occur as long as Reset is
active. Between 350 and 450 CLK2 periods after
Reset becomes inactive the Intel386 DX will start
executing instructions at the top of physical memory.
Table 2-7. Register Values after Reset
Flag Word
Machine Status Word (CR0) UUUUUUU0H Note 2
Instruction Pointer
Code Segment
Data Segment
Stack Segment
Extra Segment (ES)
Extra Segment (FS)
Extra Segment (GS)
DX register
UUUU0002H Note 1
0000FFF0H
F000H Note 3
0000H
0000H
0000H
0000H
0000H
component and
stepping ID Note 5
undefined Note 4
All other registers
NOTES:
1. EFLAG Register. The upper 14 bits of the EFLAGS reg-
ister are undefined, VM (Bit 17) and RF (BIT) 16 are 0 as
are all other defined flag bits.
2. CR0: (Machine Status Word). All of the defined fields in
the CR0 are 0 (PG Bit 31, TS Bit 3, EM Bit 2, MP Bit 1, and
PE Bit 0).
3. The Code Segment Register (CS) will have its Base Ad-
dress set to FFFF0000H and Limit set to 0FFFFH.
4. All undefined bits are Intel Reserved and should not be
used.
5. DX register always holds component and stepping iden-
tifier (see 5.7). EAX register holds self-test signature if self-
test was requested (see 5.6).
27
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