參數(shù)資料
型號: intel386 DX
廠商: Intel Corp.
英文描述: 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述: 32位CHMOS微處理器集成內(nèi)存管理(32位CHMOS微處理器帶集成存儲管理)
文件頁數(shù): 60/139頁
文件大小: 1587K
代理商: INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
8086 Application makes ‘‘Open File Call’’
x
causes
General Protection Fault (Arrow
Y
1)
Virtual 8086 Monitor intercepts call. Calls Intel386
TM
DX OS (Arrow
Y
2)
Intel386
TM
DX OS opens file returns control to 8086 OS (Arrow
Y
3)
8086 OS returns control to application. (Arrow
Y
4)
Transparent to Application
231630–70
Figure 4-25. Virtual 8086 Environment Interrupt and Call Handling
(4) Push the old 8086 stack pointer onto the new
stack by pushing the SS register (as 32-bits, high
bits undefined), then pushing the 32-bit ESP reg-
ister saved above.
(5) Push the 32-bit FLAGS register saved in step 1.
(6) Push the old 8086 instruction pointer onto the
new stack by pushing the CS register (as 32-bits,
high bits undefined), then pushing the 32-bit EIP
register.
(7) Load up the new CS:EIP value from the interrupt
gate, and begin execution of the interrupt routine
in protected Intel386 DX mode.
The transition out of virtual 8086 mode performs a
level change and stack switch, in addition to chang-
ing back to protected mode. In addition, all of the
8086 segment register images are stored on the
stack (behind the SS:ESP image), and then loaded
with null (0) selectors before entering the interrupt
handler. This will permit the handler to safely save
and restore the DS, ES, FS, and GS registers as
80286 selectors. This is needed so that interrupt
handlers which don’t care about the mode of the
interrupted program can use the same prolog and
epilog code for state saving (i.e. push all registers in
prolog, pop all in epilog) regardless of whether or not
a ‘‘native’’ mode or Virtual 8086 mode program was
interrupted. Restoring null selectors to these regis-
ters before executing the IRET will not cause a trap
in the interrupt handler. Interrupt routines which ex-
pect values in the segment registers, or return val-
ues in segment registers will have to obtain/return
values from the 8086 register images pushed onto
the new stack. They will need to know the mode of
the interrupted program in order to know where to
find/return segment registers, and also to know how
to interpret segment register values.
The IRET instruction will perform the inverse of the
above sequence. Only the extended Intel386 DXs
IRET instruction (operand size
e
32) can be used,
and must be executed at level 0 to change the VM
bit to 1.
(1) If the NT bit in the FLAGs register is on, an inter-
task return is performed. The current state is
stored in the current TSS, and the link field in the
current TSS is used to locate the TSS for the
interrupted task which is to be resumed.
Otherwise, continue with the following sequence.
(2) Read the FLAGS image from SS:8
[
ESP
]
into the
FLAGS register. This will set VM to the value ac-
tive in the interrupted routine.
(3) Pop off the instruction pointer CS:EIP. EIP is
popped first, then a 32-bit word is popped which
contains the CS value in the lower 16 bits. If
VM
e
0, this CS load is done as a protected
mode segment load. If VM
e
1, this will be done
as an 8086 segment load.
(4) Increment the ESP register by 4 to bypass the
FLAGS image which was ‘‘popped’’ in step 1.
(5) If VM
e
1, load segment registers ES, DS, FS,
and GS from memory locations SS:
[
ESP
a
8
]
,
SS:
[
ESP
a
12
]
,
SS:
[
ESP
a
16
]
,
SS:
[
ESP
a
20
]
, respectively, where the new val-
and
60
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