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| 型號(hào)： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲(chǔ)管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲(chǔ)管理） |
| 文件頁(yè)數(shù)： | 83/139頁(yè) |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
The complete bus state transition diagram, including
operation with pipelined address is given by 5-20.
Note it is a superset of the diagram for non-pipelined
address only, and the three additional bus states for
pipelined address are drawn in bold.
The fastest bus cycle with pipelined address con-
sists of just two bus states, T1P and T2P (recall for
non-pipelined address it is T1 and T2). T1P is the
first bus state of a pipelined cycle.
5.4.3.5 INITIATING AND MAINTAINING
PIPELINED ADDRESS
Using the state diagram Figure 5-20, observe the
transitions from an idle state, Ti, to the beginning of
a pipelined bus cycle, T1P. From an idle state Ti, the
first bus cycle must begin with T1, and is therefore a
non-pipelined bus cycle. The next bus cycle will be
pipelined, however, provided NA
Y
is asserted and
the first bus cycle ends in a T2P state (the address
for the next bus cycle is driven during T2P). The fast-
est path from an idle state to a bus cycle with pipe-
lined address is shown in bold below:
Ti, Ti, Ti
X Y X
states
T1 - T2 - T2P,
non-pipelined
cycle
T1P - T2P,
Y X
pipelined
cycle
Y
T1-T2-T2P are the states of the bus cycle that es-
tablishes address pipelining for the next bus cycle,
which begins with T1P. The same is true after a bus
hold state, shown below:
Th, Th, Th, T1 - T2 - T2P,
X
hold
non-pipelined
acknowledge
states
T1P - T2P,
Y X
pipelined
cycle
Y
cycle
The transition to pipelined address is shown func-
tionally by Figure 5-17 Cycle 1. Note that Cycle 1 is
used to transition into pipelined address timing for
the subsequent Cycles 2, 3 and 4, which are pipe-
lined. The NA
Y
input is asserted at the appropriate
time to select address pipelining for Cycles 2, 3
and 4.
Once a bus cycle is in progress and the current ad-
dress has become valid, the NA
Y
input is sampled
at the end of every phase one, beginning with the
next bus state, until the bus cycle is acknowledged.
During Figure 5-17 Cycle 1 therefore, sampling be-
gins in T2. Once NA
Y
is sampled asserted during
the current cycle, the Intel386 DX is free to drive a
new address and bus cycle definition on the bus as
early as the next bus state. In Figure 5-16 Cycle 1 for
example, the next address is driven during state
T2P. Thus Cycle 1 makes the transition to pipelined
address timing, since it begins with T1 but ends with
T2P. Because the address for Cycle 2 is available
before Cycle 2 begins, Cycle 2 is called a pipelined
bus cycle, and it begins with T1P. Cycle 2 begins as
soon as READY
Y
asserted terminates Cycle 1.
Example transition bus cycles are Figure 5-17 Cycle
1 and Figure 5-16 Cycle 2. Figure 5-17 shows tran-
sition during the very first cycle after an idle bus
state, which is the fastest possible transition into ad-
dress pipelining. Figure 5-16 Cycle 2 shows a tran-
sition cycle occurring during a burst of bus cycles. In
any case, a transition cycle is the same whenever it
occurs: it consists at least of T1, T2 (you assert
NA
Y
at that time), and T2P (provided the Intel386
DX has an internal bus request already pending,
which it almost always has). T2P states are repeated
if wait states are added to the cycle.
Note three states (T1, T2 and T2P) are only required
in a bus cycle performing a
transition
from non-
pipelined address into pipelined address timing, for
example Figure 5-17 Cycle 1. Figure 5-17 Cycles 2,
3 and 4 show that address pipelining can be main-
tained with two-state bus cycles consisting only of
T1P and T2P.
Once a pipelined bus cycle is in progress, pipelined
timing is maintained for the next cycle by asserting
NA
Y
and detecting that the Intel386 DX enters T2P
during the current bus cycle. The current bus cycle
must end in state T2P for pipelining to be maintained
in the next cycle. T2P is identified by the assertion of
ADS
Y
. Figures 5-16 and 5-17 however, each show
pipelining ending after Cycle 4 because Cycle 4
ends in T2I. This indicates the Intel386 DX didn’t
have an internal bus request prior to the acknowl-
edgement of Cycle 4. If a cycle ends with a T2 or
T2I, the next cycle will not be pipelined.
83
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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