參數(shù)資料
型號： intel386 DX
廠商： Intel Corp.
英文描述： 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述： 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理）
文件頁數(shù)： 70/139頁
文件大?。?/td> 1587K
代理商： INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
Effect of asserting BS16
Y
during ‘‘upper half only’’
read cycles:
Asserting BS16
Y
during ‘‘upper half only’’ reads
causes the Intel386 DX to read data on the lower
16 bits of the data bus and ignore data on the
upper 16 bits of the data bus. Data that would
have been read from D16–D31 (as indicated by
BE2
Y
and BE3
Y
) will instead be read from D0–
D15 respectively.
Effect of asserting BS16
Y
during ‘‘upper half only’’
write cycles:
Asserting BS16
Y
during ‘‘upper half only’’ writes
does not affect the Intel386 DX. When only BE2
Y
and/or BE3
Y
are asserted during a write cycle
the Intel386 DX always duplicates data signals
D16–D31 onto D0–D15 (see Table 5-1). There-
fore, no further Intel386 DX action is required to
perform these writes on 32-bit or 16-bit buses.
Effect of asserting BS16
Y
during ‘‘upper and lower
half’’ read cycles:
Asserting BS16
Y
during ‘‘upper and lower half’’
reads causes the processor to perform two 16-bit
read cycles for complete physical operand trans-
fer. Bytes 0 and 1 (as indicated by BE0
Y
and
BE1
Y
) are read on the first cycle using D0–D15.
Bytes 2 and 3 (as indicated by BE2
Y
and BE3
Y
)
are read during the second cycle, again using
D0–D15. D16–D31 are ignored during both 16-bit
cycles. BE0
Y
and BE1
Y
are always negated dur-
ing the second 16-bit cycle (See
Figure 5-14, cy-
cles 2 and 2a
).
Effect of asserting BS16
Y
during ‘‘upper and lower
half’’ write cycles:
Asserting BS16
Y
during ‘‘upper and lower half’’
writes causes the Intel386 DX to perform two
16-bit write cycles for complete physical operand
transfer. All bytes are available the first write cycle
allowing external hardware to receive Bytes 0 and
1 (as indicated by BE0
Y
and BE1
Y
) using D0–
D15. On the second cycle the Intel386 DX dupli-
cates Bytes 2 and 3 on D0–D15 and Bytes 2 and
3 (as indicated by BE2
Y
and BE3
Y
) are written
using D0–D15. BE0
Y
and BE1
Y
are always neg-
ated during the second 16-bit cycle. BS16
Y
must
be asserted during the second 16-bit cycle. See
Figure 5-14, cycles 1 and 1a
.
5.3.5 Interfacing with 32- and 16-Bit
Memories
In 32-bit-wide physical memories such as Figure 5-5,
each physical Dword begins at a byte address that is
a multiple of 4. A2–A31 are directly used as a Dword
select and BE0
Y
–BE3
Y
as byte selects. BS16
Y
is
negated for all bus cycles involving the 32-bit array.
When 16-bit-wide physical arrays are included in the
system, as in Figure 5-6, each 16-bit physical word
begins at a address that is a multiple of 2. Note the
address is decoded, to assert BS16
Y
only during
bus cycles involving the 16-bit array. (If desiring to
231630–6
Figure 5-5. Intel386
TM
DX with 32-Bit Memory
231630–7
Figure 5-6. Intel386
TM
DX with 32-Bit and 16-Bit Memory
70
相關(guān)PDF資料
PDF描述
Intel386 EX Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器)
INTEL386 SXSA 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器)
intel386 SX 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器)
INTEL386 Intel386 EX Embedded Microprocessor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
INTEL386SX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR
INTEL387 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR
INTEL387DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR
INTEL387SX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR
INTEL387TMDX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR
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