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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 55/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
4.5.4 Translation Lookaside Buffer
The Intel386 DX paging hardware is designed to
support demand paged virtual memory systems.
However, performance would degrade substantially
if the processor was required to access two levels of
tables for every memory reference. To solve this
problem, the Intel386 DX keeps a cache of the most
recently accessed pages, this cache is called the
Translation Lookaside Buffer (TLB). The TLB is a
four-way set associative 32-entry page table cache.
It automatically keeps the most commonly used
Page Table Entries in the processor. The 32-entry
TLB coupled with a 4K page size, results in cover-
age of 128K bytes of memory addresses. For many
common multi-tasking systems, the TLB will have a
hit rate of about 98%. This means that the proces-
sor will only have to access the two-level page struc-
ture on 2% of all memory references. Figure 4-22
illustrates how the TLB complements the Intel386
DX’s paging mechanism.
4.5.5 Paging Operation
231630–68
Figure 4-22. Translation Lookaside Buffer
The paging hardware operates in the following fash-
ion. The paging unit hardware receives a 32-bit lin-
ear address from the segmentation unit. The upper
20 linear address bits are compared with all 32 en-
tries in the TLB to determine if there is a match. If
there is a match (i.e. a TLB hit), then the 32-bit phys-
ical address is calculated and will be placed on the
address bus.
However, if the page table entry is not in the TLB,
the Intel386 DX will read the appropriate Page Direc-
tory Entry. If P
e
1 on the Page Directory Entry indi-
cating that the page table is in memory, then the
Intel386 DX will read the appropriate Page Table En-
try and set the Access bit. If P
e
1 on the Page
Table Entry indicating that the page is in memory,
the Intel386 DX will update the Access and Dirty bits
as needed and fetch the operand. The upper 20 bits
of the linear address, read from the page table, will
be stored in the TLB for future accesses. However, if
P
e
0 for either the Page Directory Entry or the
Page Table Entry, then the processor will generate a
page fault, an Exception 14.
The processor will also generate an exception 14,
page fault, if the memory reference violated the
page protection attributes (i.e. U/S or R/W) (e.g. try-
ing to write to a read-only page). CR2 will hold the
linear address which caused the page fault. If a sec-
ond page fault occurs, while the processor is at-
tempting to enter the service routine for the first,
then the processor will invoke the page fault (excep-
tion 14) handler a second time, rather than the dou-
ble fault (exception 8) handler. Since Exception 14 is
classified as a fault, CS: EIP will point to the instruc-
tion causing the page fault. The 16-bit error code
pushed as part of the page fault handler will contain
status bits which indicate the cause of the page
fault.
The 16-bit error code is used by the operating sys-
tem to determine how to handle the page fault Fig-
ure 4-23A shows the format of the page-fault error
code and the interpretation of the bits.
NOTE:
Even though the bits in the error code (U/S, W/R,
and P) have similar names as the bits in the Page
Directory/Table Entries, the interpretation of the er-
ror code bits is different. Figure 4-23B indicates
what type of access caused the page fault.
15
3 2 1 0
U
U U U U U U U U U U U U U U
W P
S R
Figure 4-23A. Page Fault Error Code Format
U/S
: The U/S bit indicates whether the access
causing the fault occurred when the processor was
executing in User Mode (U/S
e
1) or in Supervisor
mode (U/S
e
0)
W/R
: The W/R bit indicates whether the access
causing the fault was a Read (W/R
e
0) or a Write
(W/R
e
1)
P
: The P bit indicates whether a page fault was
caused by a not-present page (P
e
0), or by a page
level protection violation (P
e
1)
U
: UNDEFINED
55
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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