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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 69/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
231630–5
Physical Memory Space
I/O Space
NOTE:
Since A31 is HIGH during automatic communication with coprocessor, A31 HIGH and M/IO
Y
LOW can be used to
easily generate a coprocessor select signal.
Figure 5-4. Physical Memory and I/O Spaces
5.3.3 Memory and I/O Organization
The Intel386 DX datapath to memory and I/O
spaces can be 32 bits wide or 16 bits wide. When
32-bits wide, memory and I/O spaces are organized
naturally as arrays of physical 32-bit Dwords. Each
memory or I/O Dword has four individually address-
able bytes at consecutive byte addresses. The low-
est-addressed byte is associated with data signals
D0–D7; the highest-addressed byte with D24–D31.
The Intel386 DX includes a bus control input,
BS16
Y
, that also allows direct connection to 16-bit
memory or I/O spaces organized as a sequence of
16-bit words. Cycles to 32-bit and 16-bit memory or
I/O devices may occur in any sequence, since the
BS16
Y
control is sampled during each bus cycle.
See
5.3.4 Dynamic Data Bus Sizing
. The Byte En-
able signals, BE0
Y
–BE3
Y
, allow byte granularity
when addressing any memory or I/O structure,
whether 32 or 16 bits wide.
5.3.4 Dynamic Data Bus Sizing
Dynamic data bus sizing is a feature allowing direct
processor connection to 32-bit or 16-bit data buses
for memory or I/O. A single processor may connect
to both size buses. Transfers to or from 32- or 16-bit
ports are supported by dynamically determining the
bus width during each bus cycle. During each bus
cycle an address decoding circuit or the slave de-
vice itself may assert BS16
Y
for 16-bit ports, or ne-
gate BS16
Y
for 32-bit ports.
With BS16
Y
asserted, the processor automatically
converts operand transfers larger than 16 bits, or
misaligned 16-bit transfers, into two or three trans-
fers as required. All operand transfers physically oc-
cur on D0–D15 when BS16
Y
is asserted. There-
fore, 16-bit memories or I/O devices only connect
on data signals D0–D15. No extra transceivers are
required.
Asserting BS16
Y
only affects the processor when
BE2
Y
and/or BE3
Y
are asserted during the current
cycle. If only D0–D15 are involved with the transfer,
asserting BS16
Y
has no affect since the transfer
can proceed normally over a 16-bit bus whether
BS16
Y
is asserted or not. In other words, asserting
BS16
Y
has no effect when only the lower half of the
bus is involved with the current cycle.
There are two types of situations where the proces-
sor is affected by asserting BS16
Y
, depending on
which Byte Enables are asserted during the current
bus cycle:
Upper Half Only:
Only BE2
Y
and/or BE3
Y
asserted.
Upper and Lower Half:
At least BE1
Y
, BE2
Y
asserted (and perhaps
also BE0
Y
and/or BE3
Y
).
69
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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