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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 41/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
Task gates are used to switch tasks. Task gates
may only refer to a task state segment (see section
4.4.6
Task Switching
) therefore only the destination
selector portion of a task gate descriptor is used,
and the destination offset is ignored.
Exception 13 is generated when a destination selec-
tor does not refer to a correct descriptor type, i.e., a
code segment for an interrupt, trap or call gate, a
TSS for a task gate.
The access byte format is the same for all gate de-
scriptors. P
e
1 indicates that the gate contents are
valid. P
e
0 indicates the contents are not valid and
causes exception 11 if referenced. DPL is the de-
scriptor privilege level and specifies when this de-
scriptor may be used by a task (see section 4.4
Pro-
tection
). The S field, bit 4 of the access rights byte,
must be 0 to indicate a system control descriptor.
The type field specifies the descriptor type as indi-
cated in Figure 4-8.
4.3.4.7 DIFFERENCES BETWEEN Intel386
TM
DX
AND 80286 DESCRIPTORS
In order to provide operating system compatibility
between the 80286 and Intel386 DX, the Intel386
DX supports all of the 80286 segment descriptors.
Figure 4-9 shows the general format of an 80286
system segment descriptor. The only differences be-
tween 80286 and Intel386 DX descriptor formats are
that the values of the type fields, and the limit and
base address fields have been expanded for the In-
tel386 DX. The 80286 system segment descriptors
contained a 24-bit base address and 16-bit limit,
while the Intel386 DX system segment descriptors
have a 32-bit base address, a 20-bit limit field, and a
granularity bit.
By supporting 80286 system segments the Intel386
DX is able to execute 80286 application programs
on an Intel386 DX operating system. This is possible
because the processor automatically understands
which descriptors are 80286-style descriptors and
which descriptors are Intel386 DX-style descriptors.
In particular, if the upper word of a descriptor is zero,
then that descriptor is a 80286-style descriptor.
The only other differences between 80286-style de-
scriptors and Intel386 DX descriptors is the interpre-
tation of the word count field of call gates and the B
bit. The word count field specifies the number of
16-bit quantities to copy for 80286 call gates and
32-bit quantities for Intel386 DX call gates. The B bit
controls the size of PUSHes when using a call gate;
if B
e
0 PUSHes are 16 bits, if B
e
1 PUSHes are 32
bits.
4.3.4.8 SELECTOR FIELDS
A selector in Protected Mode has three fields: Local
or Global Descriptor Table Indicator (TI), Descriptor
Entry Index (Index), and Requestor (the selector’s)
Privilege Level (RPL) as shown in Figure 4-10. The
TI bits select one of two memory-based tables of
descriptors (the Global Descriptor Table or the Local
Descriptor Table). The Index selects one of 8K de-
scriptors in the appropriate descriptor table. The
RPL bits allow high speed testing of the selector’s
privilege attributes.
4.3.4.9 SEGMENT DESCRIPTOR CACHE
In addition to the selector value, every segment reg-
ister has a segment descriptor cache register asso-
ciated with it. Whenever a segment register’s con-
tents are changed, the 8-byte descriptor associated
with that selector is automatically loaded (cached)
on the chip. Once loaded, all references to that seg-
ment use the cached descriptor information instead
of reaccessing the descriptor. The contents of the
descriptor cache are not visible to the programmer.
Since descriptor caches only change when a seg-
ment register is changed, programs which modify
the descriptor tables must reload the appropriate
segment registers after changing a descriptor’s
value.
31
0
SEGMENT BASE 15 . . . 0
SEGMENT LIMIT 15 . . . 0
0
Intel Reserved
Set to 0
P
DPL
S
TYPE
BASE
23 . . . 16
a
4
BASE
LIMIT
P
Base Address of the segment
The length of the segment
Present Bit
1
e
Present
0
e
Not Present
DPL
S
TYPE
Descriptor Privilege Level 0–3
System Descriptor
Type of Segment
0
e
System
1
e
User
Figure 4-9. 80286 Code and Data Segment Descriptors
41
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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