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參數(shù)資料
| 型號： | intel386 DX |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理) |
| 中文描述： | 32位CHMOS微處理器集成內(nèi)存管理（32位CHMOS微處理器帶集成存儲管理） |
| 文件頁數(shù)： | 14/139頁 |
| 文件大?。?/td> | 1587K |
| 代理商： | INTEL386 DX |
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Intel386
TM
DX MICROPROCESSOR
SYSTEM ADDRESS REGISTERS
47 32-BIT LINEAR BASE ADDRESS 16 15
LIMIT
0
GDTR
IDTR
SYSTEM SEGMENT
REGISTERS
V
15
DESCRIPTOR REGISTERS (AUTOMATICALLY LOADED)
W
0
V
32-BIT SEGMENT LIMIT
W
32-BIT LINEAR BASE ADDRESS
ATTRIBUTES
TR
SELECTOR
LDTR
SELECTOR
Figure 2-7. System Address and System Segment Registers
LDTR and TR
These registers hold the 16-bit selector for the LDT
descriptor and the TSS descriptor, respectively.
The LDT and TSS segments, since they are task-
specific segments, are defined by selector values
stored in the system segment registers. Note that a
segment descriptor register (programmer-invisible)
is associated with each system segment register.
2.3.8 Debug and Test Registers
Debug Registers:
The six programmer accessible
debug registers provide on-chip support for debug-
ging. Debug Registers DR0–3 specify the four linear
breakpoints. The Debug Control Register DR7 is
used to set the breakpoints and the Debug Status
Register DR6, displays the current state of the
breakpoints. The use of the debug registers is de-
scribed in section 2.12
Debugging support.
DEBUG REGISTERS
31
0
LINEAR BREAKPOINT ADDRESS 0
DR0
LINEAR BREAKPOINT ADDRESS 1
DR1
LINEAR BREAKPOINT ADDRESS 2
DR2
LINEAR BREAKPOINT ADDRESS 3
DR3
Intel reserved. Do not define.
Intel reserved. Do not define.
BREAKPOINT STATUS
DR4
DR5
DR6
BREAKPOINT CONTROL
DR7
TEST REGISTERS (FOR PAGE CACHE)
31
0
TEST CONTROL
TR6
TEST STATUS
TR7
Figure 2-8. Debug and Test Registers
Test Registers:
Two registers are used to control
the testing of the RAM/CAM (Content Addressable
Memories) in the Translation Lookaside Buffer por-
tion of the Intel386 DX. TR6 is the command test
register, and TR7 is the data register which contains
the data of the Translation Lookaside buffer test.
Their use is discussed in section 2.11
Testability.
Figure 2-8 shows the Debug and Test registers.
2.3.9 Register Accessibility
There are a few differences regarding the accessibil-
ity of the registers in Real and Protected Mode. Ta-
ble 2-1 summarizes these differences. See Section
4
Protected Mode Architecture
for further details.
2.3.10 Compatibility
VERY IMPORTANT NOTE:
COMPATIBILITY WITH FUTURE PROCESSORS
In the preceding register descriptions, note cer-
tain Intel386 DX register bits are Intel reserved.
When reserved bits are called out, treat them as
fully undefined. This is essential for your soft-
ware compatibility with future processors! Fol-
low the guidelines below:
1) Do not depend on the states of any unde-
fined bits when testing the values of defined
register bits. Mask them out when testing.
2) Do not depend on the states of any unde-
fined bits when storing them to memory or
another register.
3) Do not depend on the ability to retain infor-
mation written into any undefined bits.
4) When loading registers always load the unde-
fined bits as zeros.
14
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Intel386 EX | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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