參數(shù)資料
型號： 82439TX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： System Controller(系統(tǒng)控制器)
中文描述： 256M X 8, DRAM CONTROLLER, PBGA324
封裝： BGA-324
文件頁數(shù)： 9/83頁
文件大?。?/td> 461K
代理商： 82439TX
E
82439TX (MTXC)
9
PRELIMINARY
Name
Type
Description
AHOLD
O
3.3V/2.5V
Address Hold.
The MTXC asserts AHOLD when a PCI initiator is performing a
cycle to DRAM. AHOLD is held for the duration of the PCI burst transfer. The
MTXC will negate AHOLD when the completion of the PCI to DRAM read or
write cycles complete and during PCI peer transfers. AHOLD is kept asserted
while PHLDA# is asserted (i.e., duration of PIIX4 granting).
EADS#
O
3.3V/2.5V
External Address Strobe.
Asserted by the MTXC to inquire the first level
cache when servicing PCI master references of DRAM.
BOFF#
O
3.3V/2.5V
Back Off.
Asserted by the MTXC when required to terminate a CPU cycle that
was in progress.
HITM#
I
3.3V/2.5V
Hit Modified.
Asserted by the CPU to indicate that the address presented with
the last assertion of EADS# is modified in the first level cache and needs to be
written back.
M/IO#, D/C#,
W/R#
I
3.3V/2.5V
Memory/IO; Data/Control; Write/Read.
Asserted by the CPU with ADS# to
indicate the type of cycle that the system needs to perform.
HLOCK#
I
3.3V/2.5V
Host Lock.
All CPU cycles sampled with the assertion of HLOCK# and ADS#,
until the negation of HLOCK# must be atomic, i.e. no PCI activity to DRAM is
allowed.
CACHE#
I
3.3V/2.5V
Cache.
Asserted by the CPU during a read cycle to indicate the CPU will
perform a burst line fill. Asserted by the CPU during a write cycle to indicate the
CPU will perform a burst writeback cycle. If CACHE# is asserted to indicate
cacheability, the MTXC will assert KEN# either with the first BRDY#, or with
NA# if NA# is asserted before the first BRDY#.
KEN#/INV
O
3.3V/2.5V
Ken/Invalidate.
KEN#/INV functions as both the KEN# signal during CPU read
cycles, and the INV signal during L1 snoop cycles. During CPU cycles,
KEN#/INV is normally low. KEN#/INV is driven high during the 1st BRDY# or
NA# assertion of a non-L1-cacheable CPU read cycle.
KEN#/INV is driven high(low) during the EADS# assertion of a PCI master
DRAM write(read) snoop cycle. Note that KEN#/INV operation during snoop
cycles is independent of the FLCE bit programming.
SMIACT#
I
3.3V/2.5V
System Management Interrupt Active.
This is asserted by the CPU when it is
in system management mode as a result of an SMI. This signal must be
sampled active with ADS# for the processor to access the SMM space of
DRAM, located at A0000h, after SMM space has been loaded and locked by
BIOS at system boot.
HD[63:0]
I/O
3.3V/2.5V
Host Data.
These signals are connected to the CPU data bus. These signals
have internal pull-down resistors.
NOTES:
All of the signals in the host interface are described in the Pentium Processor data sheet. The preceding table
highlights MTXC specific uses of these signals.
相關(guān)PDF資料
PDF描述
82443MX PCIset
82443ZX Intel㈢ 440ZX AGPset: Host Bridge/Controller
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82452NX Intel 450NX PCIset
82453NX Intel 450NX PCIset
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82439TXC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC)
8243-A-0632-0 制造商:AMATOM ELECTRONIC HARDWARE 功能描述:
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