參數(shù)資料
型號(hào)： 82439TX
廠商： INTEL CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： System Controller(系統(tǒng)控制器)
中文描述： 256M X 8, DRAM CONTROLLER, PBGA324
封裝： BGA-324
文件頁(yè)數(shù)： 4/83頁(yè)
文件大?。?/td> 461K
代理商： 82439TX
82439TX (MTXC)
E
4
PRELIMINARY
3.1.21. PAM
Programmable Attribute Map Registers (PAM[6:0])...............................................................34
3.1.22. DRB
DRAM Row Boundary Registers............................................................................................38
3.1.23. DRTH
DRAM Row Type Register High..........................................................................................40
3.1.24. DRTL—DRAM Row Type Register Low............................................................................................41
3.1.25. MTT
Multi-Transaction Timer Register (Reserved Test Mode Register)........................................41
3.1.26. ESMRAMC
Extended System Management RAM Control Register..............................................42
3.1.27. SMRAMC
System Management RAM Control Register................................................................43
3.1.28. MCTL
Miscellaneous Control Register............................................................................................45
4.0. FUNCTIONAL DESCRIPTION......................................................................................................................46
4.1. Host Interface..............................................................................................................................................46
4.2. Secondary Cache Interface........................................................................................................................46
4.2.1. Clock Latencies....................................................................................................................................49
4.2.2. Snoop Cycles.......................................................................................................................................49
4.2.3. DRAM Cache Second Level Cache Mode ..........................................................................................50
4.3. DRAM Interface ..........................................................................................................................................50
4.3.1. DRAM Organization.............................................................................................................................51
4.3.2. Configuration Requirements ................................................................................................................53
4.3.3. DRAM Address Translation.................................................................................................................57
4.3.4. DRAM Paging ......................................................................................................................................57
4.3.5. DRAM Types........................................................................................................................................57
4.3.5.1. FPM Mode.....................................................................................................................................57
4.3.5.2. EDO Mode ....................................................................................................................................57
4.3.5.3. SDRAM Mode...............................................................................................................................57
4.3.6. Auto Detection......................................................................................................................................59
4.3.7. DRAM Performance.............................................................................................................................59
4.3.8. DRAM Refresh.....................................................................................................................................62
4.4. PCI CLK Control (CLKRUN#).....................................................................................................................62
4.4.1. Clocking States....................................................................................................................................62
4.4.2. Operation .............................................................................................................................................62
4.5. SMRAM Memory Space .............................................................................................................................62
4.5.1. Compatible SMRAM (C_SMRAM).......................................................................................................62
4.5.2. Extended SMRAM (E_SMRAM)..........................................................................................................62
4.5.3. SMRAM Programming Considerations................................................................................................64
4.6. Low Power States.......................................................................................................................................64
4.6.1. Chip Standby........................................................................................................................................65
4.6.2. Suspend/Resume ................................................................................................................................65
4.6.2.1. Power Transition Changes............................................................................................................66
4.7. PCI Interface...............................................................................................................................................67
4.8. System Arbitration.......................................................................................................................................68
4.8.1. Priority Scheme and Bus Grant...........................................................................................................68
4.8.2. CPU Policies........................................................................................................................................70
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82439TXC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC)
8243-A-0632-0 制造商:AMATOM ELECTRONIC HARDWARE 功能描述:
8243-W 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無(wú)塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無(wú)絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋
8243-W X(25) 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube
8243-WX25 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無(wú)塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無(wú)絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋
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