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參數(shù)資料
| 型號： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數(shù)： | 46/83頁 |
| 文件大?。?/td> | 461K |
| 代理商： | 82439TX |
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82439TX (MTXC)
E
46
PRELIMINARY
4.0.
FUNCTIONAL DESCRIPTION
4.1.
Host Interface
The Host Interface of the MTXC is designed to support the Pentium microprocessor. The host interface of the
MTXC supports 60-, and 66-MHz bus speeds. The Intel 430TX PCIset supports the Pentium microprocessor
with a full 64-bit data bus, 32-bit address bus, and associated internal writeback cache logic. Host bus
addresses are decoded by the MTXC for accesses to main memory, PCI memory, and PCI I/O. The MTXC also
supports the pipelined addressing capability of the Pentium microprocessor.
4.2.
Secondary Cache Interface
The MTXC integrates a high performance writeback second level cache controller using internal/external tags
and provides a full first level and second level cache coherency mechanism. The second level cache is direct
mapped, nonsectored, and supports a writeback, no write allocate (lines are not allocated on write misses)
write policy.
The second level cache can be configured to support either a 256-KB or 512-KB cache using synchronous
pipelined burst SRAM or DRAM Cache. One additional PCIset signal (KRQAK) is required to support DRAM
Cache. 64-Mbytes cacheability coverage is obtained with 8Kx8 standard SRAM to store the tags for 256-KB
configuration. For the 512-KB configurations, a 16Kx8 standard SRAM is used to store the tags and the valid bits
for 64-MB cacheability.
A second level cache line is 32-bytes wide. In the 256-KB configurations, the second level cache contains
8K lines, while the 512-KB configurations contain 16K lines. Valid and modified status bits are kept on a per line
basis. Cacheability of the entire memory space in first level cache is supported, while only the lower 64 MB of
main memory is cacheable in the second level cache. Table 9 shows the tag sizes needed to support different
sizes of cacheability. Only main memory controlled by the MTXC DRAM interface is cached. PCI memory is not
cached.
Table 9. Cacheability
Cache Size
Tag Size
Cacheability
256 Kbytes
8K by 8 bits
64 Mbytes
512 Kbytes
16K by 8 bits (including valid bit)
64 Mbytes
The following table shows the different standard SRAM access time requirements for different host clock
frequencies.
Table 10. SRAM Access Time Requirements
Host Clock Frequency (MHz)
Pipelined Burst Clock-to-Output
Access Time (ns)
Tag RAM Cycle Time (ns)
60
10
15
66
8.5
15
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
| 8243-W | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標準包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
| 8243-W X(25) | 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube |
| 8243-WX25 | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標準包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
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