
E
82439TX (MTXC)
3
PRELIMINARY
CONTENTS
PAGE
1.0. ARCHITECTURE OVERVIEW ........................................................................................................................6
2.0. SIGNAL DESCRIPTION..................................................................................................................................8
2.1. MTXC Signals...............................................................................................................................................8
2.1.1. Host Interface.........................................................................................................................................8
2.1.2. DRAM Interface ...................................................................................................................................10
2.1.3. Secondary Cache Interface.................................................................................................................12
2.1.4. PCI Interface........................................................................................................................................13
2.1.5. Test and Clock.....................................................................................................................................14
2.1.6. Power Management.............................................................................................................................14
2.1.7. Power and Ground Pins.......................................................................................................................14
2.2. MTXC Strapping Options............................................................................................................................15
2.3. Power Planes..............................................................................................................................................15
2.4. Power Sequencing Requirements ..............................................................................................................16
2.5. Signal States During and After a Hard Reset.............................................................................................17
3.0. REGISTER DESCRIPTION ...........................................................................................................................18
3.1. I/O Mapped Registers.................................................................................................................................18
3.1.1. PM2_CNTRL
PM2 Register Block....................................................................................................19
3.1.2. CONFADD
Configuration Address Register.....................................................................................19
3.1.3. CONFDATA
Configuration Data Register.........................................................................................20
PCI Configuration Space Mapped Registers.....................................................................................................20
3.1.4. VID
Vendor Identification Register....................................................................................................23
3.1.5. DID
Device Identification Register ....................................................................................................23
3.1.6. PCICMD
PCI Command Register.....................................................................................................23
3.1.7. PCISTS
PCI Status Register ............................................................................................................24
3.1.8. RID
Revision Identification Register..................................................................................................25
3.1.9. CLASSC
Class Code Register..........................................................................................................25
3.1.10. MLT
Master Latency Timer Register...............................................................................................25
3.1.11. HEDT
Header Type Register..........................................................................................................26
3.1.12. BIST
BIST Register.........................................................................................................................26
3.1.13. ACON
Arbitration Control Register .................................................................................................26
3.1.14. PCON
PCI Control Register............................................................................................................27
3.1.15. CC
Cache Control Register.............................................................................................................27
3.1.16. CEC
Extended Cache Control Register..........................................................................................29
3.1.17. SDRAMC
SDRAM Control Register ...............................................................................................29
3.1.18. DRAMEC
DRAM Extended Control Register .................................................................................31
3.1.19. DRAMC
DRAM Control Register....................................................................................................32
3.1.20. DRAMT
DRAM Timing Register......................................................................................................33