參數(shù)資料
型號: 82439TX
廠商: INTEL CORP
元件分類: 存儲控制器/管理單元
英文描述: System Controller(系統(tǒng)控制器)
中文描述: 256M X 8, DRAM CONTROLLER, PBGA324
封裝: BGA-324
文件頁數(shù): 52/83頁
文件大小: 461K
代理商: 82439TX
82439TX (MTXC)
E
52
PRELIMINARY
32-Bit SIMM
32-Bit SIMM
MA[11:0]
32-Bit SIMM
32-Bit SIMM
WEB#
CAS[7:4]#
CAS[3:0]#
RAS[3:0]#
RAS[3:2]#
RAS[1:0]#
MD[63:0]
Host Data Bus
MTXC
HD[63:0]
WEA#
mtxc_03
Figure 6. FPM/EDO Four Row SIMM Configuration
64-Bit DIMM or S0-DIMM
MA[13:0]
WEB#
SRASB#
SCASB#
CAS/DQM[7:4]#
CAS/DQM[3:0]#
RAS/CS[3:0]#
[3:2]#
[1:0]#
MD[63:0]
Host Data Bus
MTXC
HD[63:0]
64-Bit DIMM or S0-DIMM
WEA#
SRASA#
SCASA#
CKEA
CKEB
mtxc_04
NOTES:
1.
In a configuration that supports suspend to RAM, only CKE is used. This is because CKEB is not part of the suspend well
the MTXC maintains during a suspend to RAM state.
In a desktop system that supports EDO/FPM, CKE and CKEB should be used as the second pair of MA0 and MA1 lines.
CKE is used as MAA0 and CKEB is used as MAA1. In this case, they should be evenly distributed throughout the system
along with the first pair of MA0 and MA1 lines.
2.
Figure 7. FPM/EDO/SDRAM Four Row DIMM or SO-DIMM Configuration
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