參數(shù)資料
型號： 82439TX
廠商： INTEL CORP
元件分類： 存儲控制器/管理單元
英文描述： System Controller(系統(tǒng)控制器)
中文描述： 256M X 8, DRAM CONTROLLER, PBGA324
封裝： BGA-324
文件頁數(shù)： 29/83頁
文件大?。?/td> 461K
代理商： 82439TX
E
3.1.16.
82439TX (MTXC)
29
PRELIMINARY
CEC
EXTENDED CACHE CONTROL REGISTER
Address Offset:
Default Value:
Access:
53h
14h
Read/Write, Read Only
This 8-bit register defines the refresh rate (in HCLKs) for a DRAM CACHE L2 cache implementation, if enabled.
Bit
Description
7:6
5
4:0
Reserved
DRAM CACHE L2 Present (ML2)
DRAM Cache L2 Refresh Timer (MCRT)
idle during a DRAM cache refresh sequence. The smallest value for the MRCT must be 04h;
otherwise, the MTXC will not function properly
.
The default value sets the timer refresh to 20 HCLKs.
RO.
When ML2=1, an L2 DRAM CACHE is present.
R/W.
These bits determine the time the MTXC remains
3.1.17.
SDRAMC
SDRAM CONTROL REGISTER
Address Offset:
Default Value:
Access:
54–55h
0000h
Read/Write
Bit
Description
15:9
Reserved.
8:6
Special SDRAM Mode Select (SSMS).
These bits select 1 of 4 special SDRAM modes for testing
and initialization. Note that the NOP command must be programmed first before any other command
can be issued. After the DRAM detection process has completed, bits[7:5] must remain at “000”
during normal DRAM operation.
Bits[8:6]
Mode
000
Normal SDRAM mode (default).
001
NOP Command Enable (NOPCE).
This mode forces all CPU cycles to DRAM to
generate a SDRAM NOP command on the memory interface.
010
All Banks Precharge Command Enable (ABPCE).
This setting enables a mode where
all CPU cycles to DRAM are converted to an all banks precharge command on the
memory interface. Used for BIOS Detection algorithm.
011
Mode Register Command Enable (MRCE).
This setting enables a mode where all
CPU cycles to DRAM are converted into MRS commands to the memory interface. The
command is driven on the MA[11:0] lines. MA[2:0] needs to be always driven to 010 for
burst of 4 mode. MA3 needs to be always driven to 1 for interleave wrap type mode.
MA4 needs to be driven to the value in the CAS# Latency bit. MA[6:5] needs to be
always driven to 01. MA[11:7] needs to be always driven to 00000.
The BIOS will select an appropriate host address for each Row of memory such that the
right commands are generated on the Memory Address MA[11:0] lines. The BIOS
needs to be cognizant of the mapping of the Host addresses to Memory addresses. e.g.
A Host address of 1D0h will set up the Mode registers in Row 0 of SDRAM with Burst
length of 4, Wrap type of interleaved, and CAS latency of 3.
100
CBR Cycle Enable (CBRC).
This setting enables a mode where all CPU cycles to
DRAM are converted to SDRAM CBR refresh cycles on the memory interface.
101
Reserved
11X
Reserved
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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