參數(shù)資料
型號(hào)： 82439TX
廠商： INTEL CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： System Controller(系統(tǒng)控制器)
中文描述： 256M X 8, DRAM CONTROLLER, PBGA324
封裝： BGA-324
文件頁(yè)數(shù)： 63/83頁(yè)
文件大?。?/td> 461K
代理商： 82439TX
E
operate properly above 1 Mbytes. However once this is done, then SMI handlers execute at full processor
performance.
82439TX (MTXC)
63
PRELIMINARY
An error status bit is set in the Extended SMRAM Control register if the CPU tries to access the extended
SMRAM space while SMIACT# is negated and D_OPEN bit is 0. This access is forwarded to PCI bus and may
result in a Master Abort condition.
Extended SMRAM feature allows up to 1 Mbyte of SMRAM space to be writeback cacheable. This memory
space consists of any DRAM not used by the system (as shadow space etc.) between 640 Kbytes and
1 Mbyte (this memory space is referred to as High Memory in this document), and an optional block of memory
referred to as the “TSEG”. The TSEG is either a 128 Kbyte, 256 Kbyte, 512 Kbytes, or 1 Mbytes block of
memory, as defined by TSEG_SZ[1:0] of the SMRAMC register. When TSEG is enabled, the TSEG block of
memory is disabled from the top of memory and the system BIOS should report a main memory size of
(memorize - TSEG) to the OS.
The two areas of memory available for SMRAM when Extended SMRAM is enabled are:
Physical Address
DRAM Address
100A0000h to 100FFFFFh
000A0000h to 000FFFFFh
(High Mem)
10000000h plus TOM minus TSEG_SZ
to
10000000h plus TOM
TOM minus TSEG_SZ to TOM
(TSEG)
Extended SMRAM option has the following DRAM memory available to it:
Table 19. Extended SMRAM DRAM memory regions
DRAM Area
Size/Availability
A Segment
64 Kbytes always available if enabled (i.e., H_SMRAM=1 and G_SMRAME=1)
B Segment
64 Kbytes always available if enabled (i.e., H_SMRAM=1 and G_SMRAME=1)
C Segment
64 Kbytes available if not used for shadowing (as defined by PAM register) and
enabled (i.e., H_SMRAM=1 and G_SMRAME=1)
D Segment
64 Kbytes available if not used for shadowing (as defined by PAM register) and
enabled (i.e., H_SMRAM=1 and G_SMRAME=1)
E Segment
64 Kbytes available if not used for shadowing (as defined by PAM register) and
enabled (i.e., H_SMRAM=1 and G_SMRAME=1)
F Segment
64 Kbytes only available for suspend/resume (as defined by PAM register) if enabled
(i.e., H_SMRAM=1 and G_SMRAME=1)
TSEG
128K, 256K, 512K or 1M bytes available if enabled (i.e., TSEG_EN=1 and
G_SMRAME=1)
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