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參數(shù)資料
| 型號： | 82439TX |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | System Controller(系統(tǒng)控制器) |
| 中文描述： | 256M X 8, DRAM CONTROLLER, PBGA324 |
| 封裝： | BGA-324 |
| 文件頁數(shù)： | 20/83頁 |
| 文件大?。?/td> | 461K |
| 代理商： | 82439TX |
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82439TX (MTXC)
E
20
PRELIMINARY
3.1.3.
CONFDATA
CONFIGURATION DATA REGISTER
I/O Address:
Default Value:
Access:
0CFCh
00000000h
Read/Write
CONFDATA is a 32-bit read/write window into configuration space. The portion of configuration space that is
referenced by CONFDATA is determined by the contents of CONFADD.
Bit
Descriptions
31:0
Configuration Data Window (CDW).
If bit 31 of CONFADD is 1, any I/O reference that falls in the
CONFDATA I/O space is mapped to configuration space using the contents of CONFADD.
PCI CONFIGURATION SPACE MAPPED REGISTERS
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to 256 8-bit
configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space
Configuration Read
and
Configuration Write
. While memory and I/O spaces are supported by the Pentium
microprocessor, configuration space is not supported. The PCI specification defines two mechanisms to access
configuration space, Mechanism #1 and Mechanism #2. The MTXC supports only Mechanism #1. The bus
cycles used to access MTXC internal configuration registers are described later in the PCI cycle timings section.
The configuration access mechanism makes use of the CONFADD Register and CONFDATA Register. To
reference a configuration register, a DWord I/O write cycle is used to place a value into CONFADD that specifies
the PCI bus, the device on that bus, the function within the device, and a specific configuration register of the
device function being accessed. CONFADD[31] must be 1 to enable a configuration cycle. CONFDATA then
becomes a window onto four bytes of configuration space specified by the contents of CONFADD. Any read or
write to CONFDATA will result in the MTXC translating CONFADD into a PCI configuration cycle.
Type 0 Access
If the Bus Number field of CONFADD is 0 a Type 0 Configuration cycle is performed on PCI. CONFADD[10:2] is
mapped directly to AD[10:2]. The Device Number field of CONFADD is decoded onto AD[31:11]. The MTXC is
Device #0 and does not pass its configuration cycles to PCI so AD11 will never be asserted. Device #1 will
assert AD12, Device #2 will assert AD13, and so forth up to Device #20 which will assert AD31. Only one AD
line is asserted at a time. All device numbers higher than 20 cause a type 0 configuration access with no IDSEL
asserted, which will result in a Master Abort.
Type 1 Access
If the Bus Number field of CONFADD is non-zero a Type 1 Configuration cycle is performed on PCI.
CONFADD[23:2] is mapped directly to AD[23:2]. AD[1:0] are driven to 01 to indicate a Type 1 Configuration
cycle. All other lines are driven to 0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82443MX | PCIset |
| 82443ZX | Intel㈢ 440ZX AGPset: Host Bridge/Controller |
| 82451NX | Intel 450NX PCIset |
| 82452NX | Intel 450NX PCIset |
| 82453NX | Intel 450NX PCIset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82439TXC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:INTEL 430HX PCISET 82439HX SYSTEM CONTROLLER (TXC) |
| 8243-A-0632-0 | 制造商:AMATOM ELECTRONIC HARDWARE 功能描述: |
| 8243-W | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
| 8243-W X(25) | 功能描述:化學(xué)物質(zhì) OPTICAL WIPE 25 PER BOX RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Adhesives 類型:Epoxy Compound 大小:1.7 oz 外殼:Plastic Tube |
| 8243-WX25 | 功能描述:WIPE OPTICAL INDIVIDUAL PACKS RoHS:是 類別:靜電控制，ESD，無塵室產(chǎn)品 >> 處理劑，清潔劑，擦拭布 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 處理劑/清潔劑類型:清潔布 使用:電子設(shè)備 技術(shù)規(guī)格:無絨毛，微纖維 數(shù)量:100（12" L x 12" W） 包裝:袋 |
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